Term | Meaning | Taught in |
|---|---|---|
Interrupt controller | Collects interrupt inputs, applies enable and priority and gives the CPU one request. NanoSoC takes 8 levels in and gives one level out. | |
Interrupt latency | Time from a source raising its line to the CPU seeing the request. NanoSoC irq_dma takes 135.4 ns at best and 182.3 ns at worst. | |
Interrupt wiring table | The table naming each interrupt source, its input number, polarity, clear method and priority. It is the source for the connectivity test. | |
Length agreement | The DMA LEN and the stream bridge LEN are separate registers and must hold the same word count, or the job ends in ERR or never completes. | |
Level interrupt | A request held until software clears its cause. It cannot be lost by a slow receiver, unlike a pulse shorter than the synchroniser's sampling. | |
Lost and spurious interrupt | Lost: a request that never reaches the CPU, such as a short pulse. Spurious: a request with no cause by the time software looks. | |
Pad mux (function select) | Choosing which internal function drives a package pin when several share it, with a defined reset choice. | |
Pending, enable and raw | RAW is the synchronised input level, ENABLE masks it, PENDING is RAW and ENABLE. NanoSoC TOP returns the lowest pending input. | |
Priority (fixed) | A rule for which pending interrupt is served first. NanoSoC is fixed: the lowest number wins, so the power interrupt outranks the DMA. | |
Sticky status (DONE and ERR) | Status bits that stay set until software clears them. A stale ERR keeps the interrupt high even after a good job. | |
Stream bridge (nano_sbr) | The NanoSoC block that reads memory into the DMA's input stream and writes the DMA's output stream back, as an AXI master. | |
Streaming DMA | A DMA whose data ports are streams rather than a memory bus. The NanoSoC DMA XORs each 32-bit word with a key as it passes. |
Back to the Glossary for the other groups and the look-alike terms.