Address and register sweep

A test that reads or writes every region and register and checks the reset value, access type and response against the map.

Address and Register Sweeps

Connectivity test

A test that forces each source and checks the matching destination, for example each interrupt line against its controller input.

Address-Map and Interrupt Wiring Checks

Firmware co-simulation

Running the real boot code against the RTL, so reset order, register contracts and timing are exercised the way software will use them.

Running Boot Code Against RTL

Gate-level simulation

Simulating the netlist with cell delays to find reset, X and timing problems the RTL hides.

What Gate-Level Simulation Finds

JTAG and TAP

The public test access standard, with a port controller that gives access to scan chains and debug. Its pins need safe defaults.

JTAG and Safe Defaults at Reset

Lockstep and parity

Safety mechanisms that detect a fault by comparing two copies or checking a parity bit, then report and react.

Lockstep, Parity and Redundancy

Performance counter

A hardware counter of cycles, beats or stalls on a link. A miss against the budget is read from counters first.

Performance Counters and What a Miss Looks Like

Planted bug

A deliberately introduced integration mistake used to prove a test can catch it. NanoSoC has ten.

Planted Bugs and Regression Hooks

Power-aware simulation

Simulation that switches domains off and applies isolation and retention behaviour, so power-intent mistakes show up as X.

Power-Aware Simulation and Isolation Checks

Scan chain

Flops connected into shift registers in test mode so internal state can be loaded and read. The integrator joins block chains at the top.

Scan Chains and Wrapper Cells

Self-test in ROM

Boot-code checks, such as reading DMA reset values and moving a short stream, run before the image is trusted.

Checkpoints and Self-Test in ROM

Test mode

A chip state where functional clocks and resets are replaced by test controls. Entering it needs a defined pin sequence.

Test-Mode Architecture

Top-level test list

The list of chip-level tests, each mapped to the integration bug it can catch.

The NanoSoC Top-Level Test List

X propagation

Unknown values spreading through a netlist from an unreset or unpowered source. They are a sign of a missing reset or isolation.

X-Propagation, Reset Order and Timing