Asynchronous assert, synchronous release

A reset may assert at any time but is released through a synchroniser in each domain, so it leaves reset on a clock edge that meets recovery and removal.

Asynchronous Assert, Synchronous Release

Asynchronous FIFO

A dual-clock FIFO that moves multi-bit data between unrelated clocks, with gray-coded pointers synchronised across. NanoSoC puts one on each AXI channel between the CPU and the fabric.

The Ten Crossings

Clock domain

The set of flops driven by one clock tree. NanoSoC has three: clk_cpu 192 MHz, clk_sys 96 MHz and clk_per 24 MHz.

Choosing Domains and Ratios

Clock gate (ICG)

A latch-and-AND cell that stops a clock without a glitch. Its enable must be stable during the high phase, which the latch guarantees.

ICG Cells and Enable Timing

Clock ratio

The integer relation of two frequencies. NanoSoC runs clk_cpu : clk_sys : clk_per at 8 : 4 : 1.

Choosing Domains and Ratios

Crossing

A signal that passes from one clock domain to another. NanoSoC has ten groups, each with a named mechanism.

The Ten Crossings

Glitch-free switching

Changing a clock source without producing a short pulse, by gating the old clock off and the new one on in a safe order.

Glitch-Free Switching Sequence

Handshake crossing (request and acknowledge)

A multi-bit crossing where the data is held still while a single toggled bit is synchronised, so the receiver captures only stable data. The APB bridge to clk_per uses it.

Choosing a Mechanism per Crossing

Phase-related and asynchronous

Clocks from one PLL keep an exact ratio but, with separate trees, an unbounded offset, so signoff treats them as asynchronous. clk_cpu and clk_sys are signed off that way.

Phase-Related Versus Asynchronous Signoff

PLL

A circuit that multiplies a reference clock. NanoSoC multiplies 24 MHz by 32 to a 768 MHz VCO; post-VCO dividers of 4 and 8 give 192 and 96 MHz.

Crystal, PLL and Dividers

PLL lock

The signal that the PLL output is stable. NanoSoC waits 256 clk_per cycles, 10.667 us, and the clocks stay gated until it is seen.

PLL Wrapper and the Lock Handshake

Recovery and removal

The reset-release equivalents of setup and hold: the reset must be released a minimum time before and held a minimum time after the clock edge.

Asynchronous Assert, Synchronous Release

Release order

The sequence in which domains leave reset. Slaves and fabric first, the CPU last, because the first fetch must find a fabric that is ready.

Release Order and Timing

Reset cause (RST_CAUSE)

A register recording what produced the last reset: POR, PAD, SW or WAKE. It is reset only by power-on reset, so boot code can read it.

Reset Controller Registers and Software View

Reset tree

The distribution of reset sources to the per-domain reset nets: rst_per_n, rst_sys_n and rst_cpu_n, each synchronised in its own domain.

The Reset Tree per Domain

Two-flop synchroniser

Two flops in the receiving clock that give a metastable first flop a full cycle to settle. It is correct for a single bit held for at least two receiving cycles.

Choosing a Mechanism per Crossing

Watchdog

A timer that resets or interrupts if software does not service it in time. Its reset must be wired and its cause recorded. NanoSoC v1 has none (only the bridge's 256-cycle bus watchdog); it is an extension topic.

Watchdog-to-Reset Wiring