Always-on domain (AON)

The power domain that is never switched, holding the reset and power controller, the PLL, the interrupt controller and the slow peripherals, SRAM0 retention and the ROM.

Always On Versus Switchable

Break-even time

How long a domain must stay off for the leakage saved to repay the energy of switching it off and on.

Power-Gating Saving and Break-Even

Cold start

Bringing the chip from no power to the first fetch: supplies, crystal, PLL, resets and clocks in order. NanoSoC hardware takes 53.948 us.

One Timeline from POR to First Fetch

DVFS

Changing voltage and frequency together with the state of the load. Raise voltage before frequency, lower frequency before voltage.

Raise V Then f, Lower f Then V

Dynamic power

Power from switching: roughly activity x capacitance x voltage squared x frequency. NanoSoC RUN dynamic power is 77.10 mW.

Dynamic and Leakage Roll-Up

Isolation cell

A clamp on a signal from a powered-down domain into a powered one, forcing a safe value. NanoSoC has 114, all clamping to 0.

Where the 114 Clamps Go

Leakage power

Power drawn with no switching. NanoSoC leakage is 5.64 mW in RUN and IDLE and 1.24 mW in SLEEP.

Dynamic and Leakage Roll-Up

Power domain

A region with its own supply that can be on or off independently. NanoSoC has PD_AON and the switchable PD_SW.

Always On Versus Switchable

Power good (PGOOD)

A signal that a supply has reached its operating range. The sequencer waits for it before releasing isolation and reset.

Supply Order Rules and Power-Good

Power sequencer

The state machine that orders clamp, clock gate, reset and switch on the way down and the reverse on the way up, with timeouts.

The Sequencer State Machine

Power state

A named operating condition. NanoSoC has RUN (82.74 mW), IDLE (16.89 mW) and SLEEP (1.40 mW).

RUN, IDLE and SLEEP

Retention

Keeping state while power is reduced. NanoSoC SRAM0 stays in PD_AON and sits in retention at 60% of its leakage in SLEEP.

What Is Retained and What It Costs

UPF

The public standard format for power intent: domains, supplies, switches, isolation and retention. The integrator owns that it matches the design.

UPF Intent and What the Integrator Owns