AxPROT

The protection signals on an AXI address channel. In NanoSoC bit 1 of the prot field is 0 for secure and 1 for non-secure, and the interconnect filter reads it.

The AxPROT Partition

Boot ROM

The read-only code at the reset vector. It reads the reset cause, tests the DMA, loads the second-stage image and jumps to it.

Reset Vector and Boot-Source Select

Boot-time share

The fraction of boot spent in each step. In NanoSoC the SPI image load takes 86.9% of 12.581 ms, the banner 11.0%, and hardware reset 0.43%.

Where Boot Time Really Goes

Chain of trust

Each boot stage checks the next before running it, starting from code that cannot be changed.

Chain of Trust and Immutable ROM

Debug locking

Restricting debug access by lifecycle state so a deployed chip cannot be read through its debug port.

Lifecycle States and Debug Locking

ECC

An error-correcting code stored with memory data: it corrects some errors and detects more. Parity only detects.

Parity Versus ECC

eFuse or OTP

One-time programmable storage for trim, repair data, keys and lifecycle bits, read out at boot and distributed to the blocks that use it.

What Lives in the Fuse Array

External memory controller

A block that drives off-chip memory. The integrator wires its bus, clocks and reset and owns who runs its initialisation and training.

What the Integrator Wires

Known weakness of the security partition

NanoSoC's SBR register slot is non-secure, so non-secure software can clear the NS bit and reach SRAM1 through the SBR. The partition is not closed until the NS bit is writable from the secure side only.

The Integrator Security Checklist

Memory wrapper

A thin layer around a memory macro that fixes its port, adds test, retention and power controls, and hides the macro's timing behind a standard interface.

Macro Choice and Wrappers

Reset vector

The address where the CPU fetches its first instruction. NanoSoC's is 0x0000_0000, in the boot ROM.

Reset Vector and Boot-Source Select

Root of trust

The part that cannot be changed or bypassed and on which every later check depends: the ROM, its keys and the fuse bits that select the mode.

Chain of Trust and Immutable ROM

Scrubbing

Reading and rewriting memory in the background so single errors are corrected before a second one accumulates.

Scrubbing and First Access

Secure-only region

A region that answers only accesses marked secure. NanoSoC SRAM1 and the reset and power controller are secure-only.

The AxPROT Partition

Strap pin

A pin sampled at reset to select a mode, such as the boot source.

Strap, Boot-Mode and Test Pins