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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
    • Glossary: Address and decode
    • Glossary: Interconnect
    • Glossary: Clocks and resets
    • Glossary: Power
    • Glossary: Interrupts and DMA
    • Glossary: Memory, boot and security
    • Glossary: Integration and handoff
    • Glossary: Verification, test and bring-up
    • Glossary: Package and I/O
    • Glossary: Signoff and process
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←SoC Glossary
  1. Topics
  2. SoC Design
  3. SoC Glossary
  4. Glossary: Signoff and process

SoC DesignAll levels

Glossary: Signoff and process

SoC integration glossary terms: signoff and process.

Signoff and process

Term

Meaning

Taught in

Baseline freeze

Recording the exact design, constraint and tool versions the evidence refers to, then allowing changes only through a recorded process.

Freezing a Baseline

Closure dashboard

A page with one honest metric per discipline: timing, power, physical, crossings, coverage and connectivity.

The Metrics That Matter

ECO

An engineering change after the design is frozen. A metal-only ECO changes wiring layers; a respin changes everything.

Metal-Only Against Full Respin

Erratum

A documented difference between the chip and its specification, with the software workaround.

From Bug to Erratum

Escape rate

Waivers that later caused a silicon problem divided by waivers granted over a window. It keeps the price of excuses visible.

The Escape Rate

Go and no-go

The review decision to release the design, recorded with the evidence and any accepted risks.

Go and No-Go

Integration review gate

A planned review at which the integration state is judged against stated criteria before work continues.

Integration Reviews and Gates

Milestone and freeze

A dated point at which a deliverable is complete and a category of change stops.

Milestones, Deliverables and Freezes

Readiness review

The final meeting at which each owner shows evidence for their area and the integrator calls go or no-go.

Evidence per Owner

Signoff manifest

The list of every check, result, version and waiver the chip is judged on, with a checker that compares it with the frozen baseline.

What Goes in the Manifest

Spare cells

Unused gates scattered in the layout so a late fix can be wired with a metal-only change.

Spare Cells

Waiver

A recorded decision that a reported violation is acceptable, with evidence, an owner and an expiry.

What May Be Waived

Waiver ageing

Review-by and expiry dates on every waiver. In the course's teaching rule a proven-safe waiver is reviewed at 90 days and expires at 180.

Waiver Ageing

Back to the Glossary for the other groups and the look-alike terms.

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See also

  • Glossary: Address and decode
  • Glossary: Interconnect
  • Glossary: Clocks and resets