Generated Clocks & Dividers: Expanded Case Study

Extended case study

Signoff review: generated clock reachability, divide-by mismatch, pulse width violations fails after an apparently minor change affecting Generated Clocks & Dividers.

Background

Team had closure last week on full MMMC matrix. New run shows regression clustered in one path group.

Symptoms observed

• generated clock reachability, divide-by mismatch, pulse width violations regression

• Disagreement between synth and STA WNS

• Hold violations after setup ECO

Investigation timeline

1. Hour 0: freeze netlist, SDC, SPEF, lib tags

2. Hour 1: diff constraints and run manifest

3. Hour 2: isolate corner/mode that fails

4. Hour 3: read worst path — cell vs net, clocks

5. Hour 4: classify root cause

6. Hour 5: minimal ECO or SDC fix

7. Hour 6: full regression + signoff memo

Root cause

Root cause tied to Generated Clocks & Dividers: Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Fix and validation

• Bounded ECO or audited SDC change

• Re-run report_clock -attributes, generated clock tree diagram, SDC generated_clock block

• Full MMMC + SI regression

Lessons learned

• Tag every run

• Diff constraints before blaming PD

• Setup and hold together

CASE STUDY — Generated Clocks & Dividers
baseline WNS / regressed WNS / post-fix WNS

Sequence under stress

TIMING PATH — Generated Clocks & Dividers

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: generated clock reachability, divide-by mismatch, pulse width violations

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations