Generated Clocks & Dividers: Review Checklist

Review checklist

Review Checklist for Generated Clocks & Dividers focuses on generated clock reachability, divide-by mismatch, pulse width violations. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

• SDC revision and implemented clock/exception policy are named.

• Clock/reset and CDC assumptions are reviewed.

• Path groups, IO delays, and exception rationale are documented.

• MMMC scenario list maps back to signoff requirements.

• WNS/TNS artifact stored with corner/mode/view tags.

• Owners signed: STA owner, RTL owner, clock integration owner.

Sign-off ownership

OWNERSHIP MAP — Generated Clocks & Dividers

artifact              owner
----------------      -----------------
timing report       STA owner
SDC/constraint      RTL owner
implementation      clock integration owner

Every WNS cluster needs a named owner before ECO.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations