Generated Clocks & Dividers: Debug Playbook

Debug playbook

Debug Playbook for Generated Clocks & Dividers focuses on generated clock reachability, divide-by mismatch, pulse width violations. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

STA debug is a search for the FIRST deviation, not the loudest downstream symptom. Hold failures after setup ECO are a classic example of fixing the wrong layer first.

Root-cause tree

ROOT-CAUSE TREE — Generated Clocks & Dividers

generated clock reachability, divide-by mismatch, pulse width violations looks wrong
        |
   same netlist tag?
     /        \
   no          yes
   |            |
 view/SDC     real path or
 mismatch     constraint bug
 /    \           |
lib   SPEF    delay breakdown
diff  diff    cell vs net

1. Freeze the failing netlist tag, SDC revision, and SPEF corner.

2. Find the first constraint or delay anomaly on the critical path.

3. Map the path to launch/capture clocks and path group.

4. Classify the failure: constraint bug, view mismatch, cell delay, net delay, or SI.

5. Prove the mechanism with one reduced path or isolated scenario.

6. Patch the smallest owner-controlled fix and rerun setup, hold, and MMMC.

Review memo template

STAFF STA REVIEW MEMO — Constraints & SDC Fundamentals / Generated Clocks & Dividers

1. Symptom
   - Watched metric: generated clock reachability, divide-by mismatch, pulse width violations
   - Failing scenario: <corner/mode/view>
   - Path group: <reg2reg / in2reg / reg2out / async>
   - Database tags: <netlist, SDC, SPEF, lib>

2. Mechanism hypothesis
   - Primary mechanism: Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.
   - Competing hypothesis: <constraint bug, view mismatch, cell delay, net delay, SI>
   - Missing evidence: <report_timing, clock report, constraint trace>

3. Proposed action
   - Minimal reversible change: <SDC fix, sizing, VT swap, route, useful skew>
   - Expected metric movement: <WNS/TNS delta>
   - Regression risk: hold, other corners, SI, leakage

4. Signoff
   - Re-run artifact: report_clock -attributes, generated clock tree diagram, SDC generated_clock block
   - Required owners: STA owner, RTL owner, clock integration owner
   - Final decision: ECO, waive, constraint fix, or escalate

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations