STA Mastery · All levels

Generated Clocks & Dividers: Interview Drills

Interview Drills for Generated Clocks & Dividers.

Interview drills

Interview Drills for Generated Clocks & Dividers focuses on generated clock reachability, divide-by mismatch, pulse width violations. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

diagram

PROMPT
You see generated clock reachability, divide-by mismatch, pulse width violations on Generated Clocks & Dividers. Walk through root cause and fix.

STRONG ANSWER
1. Names corner/mode/view and path group.
2. Explains Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.
3. Requests report_clock -attributes, generated clock tree diagram, SDC generated_clock block.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to upsizing cells, widening routes, or blaming tools without reading constraints and path delay.

Diagram to draw on the whiteboard

Generated clock propagation

diagram

MASTER CLK ~~~~~~~~~~~~~~~~~~~~~~~~
                |
           [divider / mux]
                |
GEN CLK   ~~~~~~|~~~~~~  (create_generated_clock)

Every downstream path must use the correct launch/capture clock.
Missing generated clock -> paths analyzed on wrong period.

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — Generated Clocks & Dividers

generated clock reachability, divide-by mismatch, pulse width violations looks wrong
        |
   same netlist tag?
     /        \
   no          yes
   |            |
 view/SDC     real path or
 mismatch     constraint bug
 /    \           |
lib   SPEF    delay breakdown
diff  diff    cell vs net

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

clock report
uncertainty budget
IO delay coverage
exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations

Practice this lesson