Generated Clocks & Dividers: Reports & Metrics

Reports and metrics

Reports & Metrics for Generated Clocks & Dividers focuses on generated clock reachability, divide-by mismatch, pulse width violations. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

The job of a report is to turn generated clock reachability, divide-by mismatch, pulse width violations into a closure decision. A single WNS number is almost never enough; you need path group breakdown, cell vs net split, and a clear gap between current slack and signoff target.

Metric movement

METRIC GRAPH — generated clock reachability, divide-by mismatch, pulse width violations

WNS (ps)
  ^
  |                         target (0)
  |                       - - - - - - -
  |                  o after ECO + hold check
  |              o
  |         o baseline run
  |    o failing regression
  +--------------------------------------> closure iteration
    view audit     path group fix     MMMC signoff

Readout:
  - explain why WNS/TNS moved and which path group drove the change

Slack distribution

SLACK HISTOGRAM — Generated Clocks & Dividers

path count
  |      ***
  |    *******
  |  ***********
  |*************  <- WNS (worst path)
  +--------------------> slack (ns)
  -0.15  0.0  0.10

Fix the left tail first; average slack misleads.

• Track generated clock reachability, divide-by mismatch, pulse width violations by path group, corner, and analysis view.

• Report WNS/TNS and failing endpoint count together.

• Include setup and hold splits; they often diverge after ECO.

• Always store the metric next to the artifact that produced it.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Reading reports