Generated Clocks & Dividers: Silicon PPA Impact

Silicon PPA and closure impact

Clock trees, uncertainty, and IO modeling drive CTS and package work.

Area drivers

• Upsize cells

• Buffer insertion

• Shield wires

Power drivers

• VT swap leakage

• Clock tree power for skew

Timing impact

• Net delay on critical routes

• SI delta delay

PD consequences

• Congestion limits sizing

• Layer promotion for nets

Verification burden

• ECO equivalence

• SI re-signoff

PPA — Generated Clocks & Dividers
area/power/timing/closure-time tradeoff

PPA takeaways

• ECO has PPA cost

• Signoff is multi-corner

Design option PPA snapshot

BEFORE / AFTER ECO — Generated Clocks & Dividers

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations