Generated Clocks & Dividers: Software / Programmer View

RTL / implementation view

RTL clocking and boundary design determine what SDC can legally express.

What designers feel

• Surprise timing after RTL 'small' change

• Clock domain bugs

RTL structure impact

• Pipeline depth

• Reset and clock gating

• Boundary flop placement

Synthesis interaction

• Retiming constraints

• Don't care optimization vs STA

RTL-side mitigations

• Register boundaries

• Clean clocking

• Review SDC with RTL changes

RTL — Generated Clocks & Dividers
// pipeline stage added -> check new reg2reg path group WNS

Layer the driver touches

STA OWNERSHIP LAYERS — Generated Clocks & Dividers

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations