Generated Clocks & Dividers: Step-by-Step Walkthrough

Step-by-step analysis walkthrough

Use when you own Generated Clocks & Dividers in a timing war room.

1. Open signoff scenario list — note worst WNS corner.

2. report_timing -max/-min on failing group.

3. Trace launch and capture clocks on critical path.

4. Check exceptions and generated clocks on path.

5. Break down cell vs net delay.

6. Compare implementation vs signoff view if delta suspicious.

7. Assign owner: RTL, synth, PD, CTS, SI.

8. Propose ECO with hold/SI check plan.

9. Run regression matrix.

10. Update closure dashboard and memo.

Artifacts to collect

• report_clock -attributes, generated clock tree diagram, SDC generated_clock block

• SDC file

• SPEF tag

• MMMC scenario list

• ECO ticket

Decision memo template

STA DECISION MEMO — Generated Clocks & Dividers
corner/mode:
WNS/TNS:
hypothesis:
ECO:
regression:
owners: STA owner, RTL owner, clock integration owner

Reference visuals

Generated clock propagation

MASTER CLK ~~~~~~~~~~~~~~~~~~~~~~~~
                |
           [divider / mux]
                |
GEN CLK   ~~~~~~|~~~~~~  (create_generated_clock)

Every downstream path must use the correct launch/capture clock.
Missing generated clock -> paths analyzed on wrong period.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations