Generated Clocks & Dividers: Theory Deep Dive

Foundational theory

Generated Clocks & Dividers is central to Constraints & SDC Fundamentals. Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping. Senior STA engineers always tie slack movement to corner, mode, constraint set, and parasitic view — not just a single report line.

Core concepts explained

• Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

• Primary metric: generated clock reachability, divide-by mismatch, pulse width violations

• Primary artifact: report_clock -attributes, generated clock tree diagram, SDC generated_clock block

• Owners: STA owner, RTL owner, clock integration owner

• Setup: max delay path; Hold: min delay path

• WNS/TNS summarize tail risk across endpoints

Why this matters at signoff

At signoff, Generated Clocks & Dividers failures block tapeout or force risky ECO. SDC is the contract between RTL intent, synthesis, and signoff STA. Wrong analysis setup wastes weeks of PD effort.

Mental model

MASTER CLK ~~~~~~~~~~~~~~~~~~~~~~~~
                |
           [divider / mux]
                |
GEN CLK   ~~~~~~|~~~~~~  (create_generated_clock)

Every downstream path must use the correct launch/capture clock.
Missing generated clock -> paths analyzed on wrong period.

Worked intuition

1. Name corner, mode, and view for the failing run.

2. Open generated clock reachability, divide-by mismatch, pulse width violations and identify worst path group.

3. Read critical path: cell vs net, launch/capture clocks.

4. Check constraints on that path (exceptions, generated clocks).

5. Collect report_clock -attributes, generated clock tree diagram, SDC generated_clock block and tag database versions.

6. Classify: constraint bug, view mismatch, or real path.

7. Propose minimal ECO and list MMMC+SI regression.

Common misconceptions

• One typical corner is enough for signoff.

• False paths can be applied broadly to green-wash violations.

• Implementation WNS equals signoff WNS without view mapping.

• Setup fix automatically preserves hold.

Visual reinforcement

Generated clock propagation

MASTER CLK ~~~~~~~~~~~~~~~~~~~~~~~~
                |
           [divider / mux]
                |
GEN CLK   ~~~~~~|~~~~~~  (create_generated_clock)

Every downstream path must use the correct launch/capture clock.
Missing generated clock -> paths analyzed on wrong period.

Layer responsibilities

STA OWNERSHIP LAYERS — Generated Clocks & Dividers

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Theory reinforcement

SDC is the contract between RTL intent, synthesis, and signoff STA.