Generated Clocks & Dividers: Worked Example

Worked example

Worked Example for Generated Clocks & Dividers focuses on generated clock reachability, divide-by mismatch, pulse width violations. The goal is to connect the observable symptom to timing mechanism, ownership, and regression risk.

A signoff run shows generated clock reachability, divide-by mismatch, pulse width violations. The first review mistake is to blame implementation without checking constraints. A better review starts by pinning one critical path, proving where slack was lost, and checking whether the SDC rule is correct for Generated Clocks & Dividers.

Sequence under inspection

TIMING PATH — Generated Clocks & Dividers

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: generated clock reachability, divide-by mismatch, pulse width violations

Generated clock propagation

MASTER CLK ~~~~~~~~~~~~~~~~~~~~~~~~
                |
           [divider / mux]
                |
GEN CLK   ~~~~~~|~~~~~~  (create_generated_clock)

Every downstream path must use the correct launch/capture clock.
Missing generated clock -> paths analyzed on wrong period.

1. Capture report_timing and the relevant SDC excerpt.

2. Tag corner, mode, view, and path group.

3. Find the first cell or net that dominates critical delay.

4. Compare against report_clock -attributes, generated clock tree diagram, SDC generated_clock block.

5. Choose one reversible ECO and write the regression matrix before editing netlist or constraints.

Did the fix work?

BEFORE / AFTER ECO — Generated Clocks & Dividers

WNS (ps)
  0 |                    --- target
-50 |    ● regressed
-80 |         ● before ECO
-20 |              ● after ECO
    +-------------------------------> ECO iteration
Prove setup AND hold moved safely.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.

Principal STA review addendum

Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping.

Metric: generated clock reachability, divide-by mismatch, pulse width violations