Part 2 · Phases & Lifecycle · Intermediate

Mid-Simulation Reset Flow: Soft-Reset Test Walkthrough

End-to-end soft-reset scenario: initial traffic, trigger reset, jump to reset_phase, verify recovery traffic.

Test scenario

Verify DUT recovery after a soft reset triggered mid-test: run traffic, assert soft reset, jump to reset_phase, run post-recovery traffic, check both phases produced expected results.

diagram

[PHASE][UVM] soft-reset test flow

main_phase:
  1) pre-reset traffic (objection raised)
  2) trigger soft reset condition
  3) drain in-flight transactions
  4) phase.jump(reset_phase)
  5) post-recovery traffic
  6) drop objection

check_phase:
  verify pre-reset AND post-recovery txn counts

Reference implementation

systemverilog

class soft_reset_test extends base_test;
  `uvm_component_utils(soft_reset_test)

  task main_phase(uvm_phase phase);
    phase.raise_objection(this, "soft reset test");

    `uvm_info("TEST", "phase 1: pre-reset traffic", UVM_MEDIUM)
    pre_reset_seq.start(env.vseqr);

    `uvm_info("TEST", "phase 2: trigger soft reset", UVM_MEDIUM)
    env.trigger_soft_reset();

    env.drain_all_agents();   // wait for in-flight completion

    `uvm_info("TEST", "phase 3: jump to reset_phase", UVM_MEDIUM)
    phase.jump(uvm_reset_phase::get());

    `uvm_info("TEST", "phase 4: post-recovery traffic", UVM_MEDIUM)
    post_recovery_seq.start(env.vseqr);

    phase.drop_objection(this, "soft reset test done");
  endtask

  function void check_phase(uvm_phase phase);
    super.check_phase(phase);
    if (env.pre_reset_txns == 0)
      `uvm_error("CHECK", "no pre-reset traffic")
    if (env.post_recovery_txns == 0)
      `uvm_error("CHECK", "no post-recovery traffic")
  endfunction
endclass

systemverilog

// Env drain helper
task drain_all_agents();
  fork
    axi_agent.wait_idle();
    apb_agent.wait_idle();
  join
  `uvm_info("DRAIN", "all agents idle", UVM_MEDIUM)
endtask

Key takeaways

Soft-reset tests need explicit pre- and post-recovery checks.
Drain agents before jump — non-negotiable for stable recovery.
Log each flow phase for debuggable jump tests.

Common pitfalls

No post-recovery traffic check — jump path never verified.
Drain skipped — scoreboard counts corrupt after jump.
Soft reset triggered while sequences still hold sequencer lock.

Sequence idempotency

After jump, configure_phase and main_phase run again. Sequences and env config must tolerate second execution — use flags or clear state in reset_phase.

systemverilog

task reset_phase(uvm_phase phase);
  super.reset_phase(phase);
  cfg.programming_done = 0;   // allow configure to re-run
  scb.flush();                // clear stale compare state
endtask

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