Part 2 · Phases & Lifecycle · Intermediate

Reset Integration Patterns: Env and Test Templates

Reusable env patterns for reset generation, agent idle contracts, drain helpers, and jump-capable base tests.

Layered reset ownership

diagram

[PHASE][UVM] reset responsibility split

TB top / env:
  owns rst_n generation, power-good, clock enable

agents (active):
  drive interface idle, wait rst_n release

agents (passive):
  flush queues, wait rst_n release

test:
  triggers soft reset via env API
  calls phase.jump when appropriate

Base env template

systemverilog

class reset_capable_env extends uvm_env;
  `uvm_component_utils(reset_capable_env)
  virtual dut_if vif;
  int pre_reset_txns, post_recovery_txns;

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    uvm_config_db#(virtual dut_if)::get(this, "", "vif", vif);
  endfunction

  task reset_phase(uvm_phase phase);
    phase.raise_objection(this, "env reset");
    apply_power_on_reset();
    phase.drop_objection(this, "env reset done");
  endfunction

  task apply_power_on_reset();
    vif.rst_n <= 0;
    repeat (10) @(posedge vif.clk);
    vif.rst_n <= 1;
    repeat (5) @(posedge vif.clk);
  endtask

  task trigger_soft_reset();
    `uvm_info("RST", "asserting soft reset", UVM_MEDIUM)
    vif.soft_rst <= 1;
    @(posedge vif.clk);
    vif.soft_rst <= 0;
    repeat (5) @(posedge vif.clk);
  endtask

  task drain_all_agents();
    // override in extended env
  endtask
endclass

systemverilog

class jump_base_test extends uvm_test;
  task run_jump_test(uvm_phase phase, uvm_sequence base_seq);
    phase.raise_objection(this);
    base_seq.start(env.vseqr);
    if (cfg.enable_jump) begin
      env.drain_all_agents();
      phase.jump(uvm_reset_phase::get());
      base_seq.start(env.vseqr);
    end
    phase.drop_objection(this);
  endtask
endclass

Key takeaways

Centralize reset generation in env; agents drive idle and wait.
Expose trigger_soft_reset() and drain_all_agents() for jump tests.
Track pre/post txn counters for recovery verification.

Common pitfalls

Each agent generating its own rst_n — races and misalignment.
No drain helper — every jump test reinvents wait logic.

Scoreboard flush contract

systemverilog

task reset_phase(uvm_phase phase);
  super.reset_phase(phase);
  scb.flush_queues();
  scb.mismatch_count = 0;  // only if test requires clean slate
endtask

Decide whether scoreboard state survives jump (cumulative) or flushes (per-segment). Document the choice in the test plan.

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