Rapid-fire questions an interviewer asks around Bus and Interface Protocol Puzzles. Answer out loud, then check yourself.
Answer: If VALID waited for READY and READY waited for VALID, both would stay low after reset and nothing would move. The protocol breaks the symmetry by letting only the receiver wait: READY may be a function of VALID, VALID may not be a function of READY.
Trap: Declaring a receiver that waits for VALID illegal.
Answer: No. A registered-ready one-entry stage is legal; it only halves the bandwidth. Throughput needs its own check, or a skid buffer or a two-entry stage in the design.
Trap: Assuming that clean data means a correct implementation.
Answer: Only in the last cycle of a transfer (PSEL, PENABLE and PREADY all high). An error response does not guarantee that the target kept its old value, so a model should not assume no change.
Trap: Sampling PSLVERR in wait states or treating an error write as a no-op.
Answer: No. AXI4 removed WID and write interleaving: W beats follow the order of the AW commands, and WLAST ends each burst. W data may arrive before its AW handshake.
Trap: Looking for WID (an AXI3 signal) or requiring AW before W.
Answer: The 5-beat burst ends at 0x1003 and crosses 0x1000; the 4-beat burst ends exactly at 0x0FFF and is legal. The rule is about the last byte address, not only the start.
Trap: Judging by AWLEN alone, or by whether the start address is near the boundary.
Answer: A cyclic wait can fill any finite buffer. The cycle must be broken with a reserved resource (escape slot or virtual channel), credits that reserve space before sending, or an acyclic acquisition order.
Trap: Treating deadlock as a sizing problem.