Four study days a week and one review day, weekends free. Each study day takes one or more topics, about an hour.
Review day: re-do every puzzle you scored 2 or lower, then the Q&A and scenario pages listed for that week.
Attempt every puzzle cold with the timer for its difficulty, score it 0 to 4, then read the solution, the checked-by line and the trap. See the difficulty guide.
E, M and H after a link mean easy, medium and hard. The plan is generated from the course data: if a section is added, the days re-balance.
Week | Day | Topics | Puzzles |
|---|---|---|---|
Week 1 | Day 1 | SystemVerilog Language Puzzles: Datatype and Bit Puzzles; SystemVerilog Language Puzzles: Fork Join Puzzles | 12 |
Week 1 | Day 2 | SystemVerilog Language Puzzles: Queue and Array Puzzles; SystemVerilog Language Puzzles: String and Casting Puzzles; OOP & Testbench Puzzles: Handle and Copy Puzzles | 18 |
Week 1 | Day 3 | OOP & Testbench Puzzles: Virtual Method Puzzles; OOP & Testbench Puzzles: Parameterized Class Puzzles; OOP & Testbench Puzzles: Factory Override Puzzles | 18 |
Week 1 | Day 4 | Concurrency & Timing Puzzles: Event Scheduling Puzzles; Concurrency & Timing Puzzles: Race Condition Puzzles; Concurrency & Timing Puzzles: Clocking Block Puzzles | 18 |
Week 1 | Day 5 (review) | SystemVerilog Language Puzzles Q&A; OOP & Testbench Puzzles Q&A; Concurrency & Timing Puzzles Q&A; Re-do every puzzle scored 2 or lower this week. | - |
Week 2 | Day 1 | Concurrency & Timing Puzzles: Semaphore & Mailbox Puzzles; Randomization & Constraint Puzzles: Constraint Solving Order Puzzles | 12 |
Week 2 | Day 2 | Randomization & Constraint Puzzles: Distribution Puzzles (dist, := vs :/); Randomization & Constraint Puzzles: solve...before Bias Puzzles; Randomization & Constraint Puzzles: randomize() with Puzzles | 18 |
Week 2 | Day 3 | SVA Assertion Puzzles: Sequence Puzzles; SVA Assertion Puzzles: Implication Puzzles; SVA Assertion Puzzles: Temporal Corner Puzzles | 18 |
Week 2 | Day 4 | SVA Assertion Puzzles: Assertion Debug Puzzles; Functional Coverage Puzzles: Covergroup and Coverpoint Puzzles; Functional Coverage Puzzles: Cross Coverage Puzzles | 18 |
Week 2 | Day 5 (review) | Concurrency & Timing Puzzles Q&A; Randomization & Constraint Puzzles Q&A; SVA Assertion Puzzles Q&A; Functional Coverage Puzzles Q&A; Framework for any unseen puzzle; Re-do misses from weeks 1 and 2. | - |
Week 3 | Day 1 | Functional Coverage Puzzles: Coverage Options Puzzles; Functional Coverage Puzzles: Coverage Closure and Sampling Timing Puzzles | 12 |
Week 3 | Day 2 | Logic & Aptitude Puzzles: Classic Brain Teasers; Logic & Aptitude Puzzles: Probability Puzzles; Logic & Aptitude Puzzles: Digital Logic Puzzles | 18 |
Week 3 | Day 3 | Logic & Aptitude Puzzles: Debugging Riddles; Scenario & Debug Puzzles: Testbench Debug Puzzles: Why Did the Test Hang?; Scenario & Debug Puzzles: Deadlock Scenario Puzzles: Objection and Phase Stalls | 18 |
Week 3 | Day 4 | Scenario & Debug Puzzles: Scoreboard Puzzles: Mismatch or Ordering Bug?; Scenario & Debug Puzzles: Real Interview Rounds: End-to-End Debug Walkthrough; UVM Testbench Puzzles: UVM Phases and Objections | 18 |
Week 3 | Day 5 (review) | Functional Coverage Puzzles Q&A; Logic & Aptitude Puzzles Q&A; Scenario & Debug Puzzles Q&A; UVM Testbench Puzzles Q&A; Testbench Hang; Constraint No-Solution; Vacuous Assertion Pass; Re-do misses from weeks 1 to 3. | - |
Week 4 | Day 1 | UVM Testbench Puzzles: Factory and config_db; UVM Testbench Puzzles: Sequences and Sequencers | 12 |
Week 4 | Day 2 | UVM Testbench Puzzles: Analysis, Scoreboards and RAL; Clock, Reset & CDC Puzzles: Reset Puzzles; Clock, Reset & CDC Puzzles: Clock Gating & Clock Mux Puzzles | 18 |
Week 4 | Day 3 | Clock, Reset & CDC Puzzles: CDC Basics Puzzles; Clock, Reset & CDC Puzzles: Verifying CDC & Reset Puzzles; Bus and Interface Protocol Puzzles: Valid/Ready Handshake Puzzles | 18 |
Week 4 | Day 4 | Bus and Interface Protocol Puzzles: APB Protocol Puzzles; Bus and Interface Protocol Puzzles: AXI Protocol Puzzles; Bus and Interface Protocol Puzzles: FIFO, Arbitration and Credit Puzzles | 18 |
Week 4 | Day 5 (review) | Cheatsheet; Coverage Not Closing; Race That Only Shows on Silicon-Like Gate-Level Timing; Coverage Closed at 100 Percent but a Bug Escaped; Full mock round: three random puzzles per section, timed, scored, out loud. | - |