Reset looks trivial until you ask which edge sees it, who sees it first, and what the flops hold before it arrives. These puzzles cover asynchronous versus synchronous assertion, the reset synchroniser, ordering across reset domains, power-on state and the first cycles after release.
1. A Reset Pulse Between Two Clock Edges [Easy]
2. The Counter Nobody Reset [Easy]
3. Asynchronous Assert, Synchronous Release [Medium]
4. Reset Has Lower Priority Than Enable [Easy]
5. Reset Release Order Across Domains [Medium]
6. Reset Released With a Blocking Assignment [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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requirements decode --> constraints/assumptions --> solve strategy
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+------------------> corner cases ---------> final answer
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explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.