Rapid-fire questions an interviewer asks around Clock, Reset & CDC Puzzles. Answer out loud, then check yourself.
Answer: Asserting asynchronously puts every flop in reset even if the clock is stopped, while releasing through two clocked flops makes the release arrive at a clock edge, so all flops in the domain leave reset together with recovery margin.
Trap: Saying the synchroniser delays the assertion by two cycles: only the release is delayed.
Answer: Nothing: RTL simulation is zero-delay and idealised, so each capture resolves to a clean old or new value. A CDC bug shows only as latency, which is why structural CDC analysis, MTBF models and gate-level checks are needed.
Trap: Reading a clean waveform as proof of a safe crossing.
Answer: MTBF grows as exp(tr/tau): an extra stage adds a clock period to tr and multiplies the MTBF by an exponential factor, while halving the data rate only doubles it (linear dependence).
Trap: Treating the gain of an extra stage as additive or linear.
Answer: The enable changes just after the rising edge while the clock is still high, so the AND output is cut or created mid-pulse. Zero-delay RTL has no clock-to-q, so the change coincides with the edge and the pulse looks clean. A latch (or an ICG cell) holds the enable through the high phase.
Trap: Assuming a synchronous source makes the enable glitch-free.
Answer: Only one bit changes per step, so a skewed or late capture gives the old or the new pointer, never a wild value. It works only for sequences that move by one and whose length is a power of two; arbitrary jumps still need a handshake.
Trap: Believing gray code makes any multi-bit bus safe.
Answer: That it actually ran: count executions or use a cover, and make sure reset itself is a known 0 or 1. An if on an X condition is false, so the checker, and the DUT's own reset, can be skipped together while the run looks clean.
Trap: Treating zero failures as success without counting how many checks executed.