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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
    • Reset Puzzles
    • Clock Gating & Clock Mux Puzzles
    • CDC Basics Puzzles
      • MTBF Of Two Flops Versus Three
      • Back-to-Back Events Through a Toggle Synchroniser
      • Why Gray Code Across Clock Domains
      • A Four-Phase Handshake For a Bus
      • Full or Not in a Gray-Coded FIFO
      • Valid Crossed, Data Did Not
    • Verifying CDC & Reset Puzzles
    • Clock, Reset & CDC Puzzles: Tricky Q&A
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Clock, Reset & CDC Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Clock, Reset & CDC Puzzles
  4. CDC Basics Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    CDC Basics Puzzles

    Single-bit and multi-bit crossings, the arithmetic of metastability, and the structures that make data safe to use on the other side: toggle synchronisers, gray code, handshakes, FIFO pointers and data coherency.

    • 6topics
    • 6lessons

    Topics in this section

    1. 1MTBF Of Two Flops Versus Three1 lesson
    2. 2Back-to-Back Events Through a Toggle Synchroniser1 lesson
    3. 3Why Gray Code Across Clock Domains1 lesson
    4. 4A Four-Phase Handshake For a Bus1 lesson
    5. 5Full or Not in a Gray-Coded FIFO1 lesson
    6. 6Valid Crossed, Data Did Not1 lesson

    About this puzzle set

    Single-bit and multi-bit crossings, the arithmetic of metastability, and the structures that make data safe to use on the other side: toggle synchronisers, gray code, handshakes, FIFO pointers and data coherency.

    Puzzles in this topic

    Diagram
    1. MTBF Of Two Flops Versus Three  [Medium]
    2. Back-to-Back Events Through a Toggle Synchroniser  [Medium]
    3. Why Gray Code Across Clock Domains  [Easy]
    4. A Four-Phase Handshake For a Bus  [Hard]
    5. Full or Not in a Gray-Coded FIFO  [Hard]
    6. Valid Crossed, Data Did Not  [Easy]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    VLSI DV interview puzzle flow

    Diagram
    VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
    
    puzzle prompt
        |
        v
    requirements decode --> constraints/assumptions --> solve strategy
             |                          |                     |
             |                          v                     v
             +------------------> corner cases ---------> final answer
                                         |
                                         v
                                  explain trade-offs
    
    Use section visuals when available; fallback preserves reasoning flow.

    Related topics

    • Clock, Reset & CDC Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: MTBF Of Two Flops Versus Three

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    See also

    • Reset Puzzles
    • Clock Gating & Clock Mux Puzzles
    • Verifying CDC & Reset Puzzles