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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
    • Valid/Ready Handshake Puzzles
    • APB Protocol Puzzles
    • AXI Protocol Puzzles
    • FIFO, Arbitration and Credit Puzzles
    • Bus and Interface Protocol Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←DV Interview Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Bus and Interface Protocol Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    Bus and Interface Protocol Puzzles

    Interview puzzles on the protocols a DV engineer is asked about: valid/ready handshakes (stall, drop, skid buffers), AMBA APB, AXI4 channels, ordering and burst rules, and FIFO, arbitration and credit flow control. Every puzzle fixes the protocol version, and every answer was reproduced with a small simulation or model.

    • 5topics
    • 25lessons

    Topics in this section

    1. 1Valid/Ready Handshake Puzzles6 lessons
      • Counting Transfers in a Valid/Ready Trace
      • Which Cycle Drops VALID Illegally?
      • Payload Changes While Stalled
      • Both Sides Wait: The Handshake Deadlock
      • Registered READY Overflows a FIFO
      • Register Slice: 50% Throughput Without Data Errors
    2. 2APB Protocol Puzzles6 lessons
      • Setup, Access and Completed Transfers
      • Two Wait States: Total Cycles and Write Moment
      • When Is PSLVERR Real?
      • Can Two Transfers Fit in Three Cycles?
      • Write Data Changes in a Wait State
      • Sampling PRDATA One Cycle Too Early
    3. 3AXI Protocol Puzzles6 lessons
      • The 4 KB Rule Splits a Burst
      • OKAY, SLVERR or DECERR?
      • WRAP Burst Address Sequence
      • WLAST One Beat Early
      • How Many Read Orders Are Legal?
      • Whose Data Is This? W Has No ID
    4. 4FIFO, Arbitration and Credit Puzzles6 lessons
      • Sizing a FIFO for a Rate Mismatch Burst
      • Empty and Full With Simultaneous Read and Write
      • Full and Empty From Gray-Coded Pointers
      • Round-Robin Grants and the Starved Requester
      • Credit Window vs Round-Trip Time
      • Circular Wait Between Two Full Queues
    5. 5Bus and Interface Protocol Puzzles: Tricky Q&A1 lesson

    What this section covers

    Interview puzzles on the protocols a DV engineer is asked about: valid/ready handshakes (stall, drop, skid buffers), AMBA APB, AXI4 channels, ordering and burst rules, and FIFO, arbitration and credit flow control. Every puzzle fixes the protocol version, and every answer was reproduced with a small simulation or model.

    Topics

    Diagram
    Valid/Ready Handshake Puzzles — 6 puzzles
    APB Protocol Puzzles — 6 puzzles
    AXI Protocol Puzzles — 6 puzzles
    FIFO, Arbitration and Credit Puzzles — 6 puzzles

    How to practice

    1. Open each topic and attempt every puzzle cold, writing your predicted answer first.

    2. Only then read the step-by-step solution and confirm the exact answer.

    3. Re-read the 'why candidates get it wrong' note — that is the actual interview signal.

    4. Finish with the section Q&A to rehearse explaining the rule out loud.

    Related topics

    • VLSI DV Interview Puzzles hub

    PreviousNext: Valid/Ready Handshake Puzzles

    Up next

    Up nextValid/Ready Handshake Puzzles

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    See also

    • How to Use This Puzzle Bank
    • SystemVerilog Language Puzzles
    • Difficulty Guide