Difficulty: Hard · Puzzle 6 of 6 · Topic: AXI Protocol Puzzles
AXI4 (not AXI3). Two write bursts are outstanding: AW#0 has AWID=5, AWLEN=1 (2 beats); AW#1 has AWID=9, AWLEN=1. The master drives W beats d0..d3 as shown; WLAST marks the last beat of each burst. Note that d2 appears BEFORE the AW#1 handshake. Which AWID does each W beat belong to? Is the order of this trace legal?
`timescale 1ns/1ns
module tb;
localparam int N = 6;
// channel activity per cycle: cycle: 012345
localparam bit [0:N-1] AWVALID = 6'b100010; // AW#0 (ID 5, len 1) at cycle 0, AW#1 (ID 9, len 1) at cycle 4
localparam bit [0:N-1] WVALID = 6'b011101; // W beats at cycles 1,2,3,5 : AW#1 has not even been issued at cycle 3
localparam bit [0:N-1] WLAST = 6'b001001; // beats d1 (cycle 2) and d3 (cycle 5) are last beats
int awid [2] = '{5, 9};
int awlen[2] = '{1, 1};
bit clk = 0;
int cyc = 0, aw_n = 0, w_n = 0, burst = 0, beat = 0;
int owner[4]; // burst number of each W beat, in arrival order
always #5 clk = ~clk;
always @(posedge clk) begin
if (AWVALID[cyc]) begin
$display("cycle %0d: AW #%0d accepted, AWID=%0d AWLEN=%0d", cyc, aw_n, awid[aw_n], awlen[aw_n]);
aw_n++;
end
if (WVALID[cyc]) begin
// a W beat carries no ID: it belongs to the oldest write burst whose W beats are not complete
owner[w_n] = burst;
$display("cycle %0d: W beat d%0d (WLAST=%0b)", cyc, w_n, WLAST[cyc]);
w_n++;
if (WLAST[cyc]) begin burst++; beat = 0; end else beat++;
end
if (cyc == N-1) begin
for (int i = 0; i < 4; i++) $display("d%0d belongs to AWID %0d", i, awid[owner[i]]);
end
cyc <= cyc + 1;
end
initial #(10*N) $finish;
endmoduleAXI4 has no WID. How does a slave know which AW a W beat belongs to?
1) AXI4 removed WID and write interleaving: W data must follow the order of the AW commands.
2) d0 and d1 (WLAST on d1) complete the first burst, which is AW#0 (ID 5).
3) d2 and d3 (WLAST on d3) belong to the next burst, AW#1 (ID 9).
4) d2 arriving before AW#1 is accepted is legal: a master may send write data before or in the same cycle as its address, and the slave must be prepared (or hold it off with WREADY).Answer: d0 and d1 belong to AWID 5; d2 and d3 belong to AWID 9. The trace is legal, including W data ahead of its AW.
Checked by running the code in Verilator 5; the printed output supports the answer above. Ownership is derived from burst order and WLAST only: d2 is attributed to AWID 9 although it arrives a cycle before that AW is accepted.
Looking for an ID on the W channel (that is AXI3's WID). In AXI4 the only link between W and AW is order plus WLAST. The second trap is thinking W must wait for AW: a monitor that requires AW before W falsely fails legal traffic from a master that issues them independently.
Why did AXI4 drop write data interleaving and WID? Model answer: The feature cost interconnect complexity (per-ID write buffers) and almost no real slave used it, so AXI4 requires write data in the same order as the addresses and removes WID; reads keep interleaving across IDs through RID.