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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
    • Valid/Ready Handshake Puzzles
    • APB Protocol Puzzles
    • AXI Protocol Puzzles
      • The 4 KB Rule Splits a Burst
      • OKAY, SLVERR or DECERR?
      • WRAP Burst Address Sequence
      • WLAST One Beat Early
      • How Many Read Orders Are Legal?
      • Whose Data Is This? W Has No ID
    • FIFO, Arbitration and Credit Puzzles
    • Bus and Interface Protocol Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Bus and Interface Protocol Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Bus and Interface Protocol Puzzles
  4. AXI Protocol Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    AXI Protocol Puzzles

    AXI4 channel independence, per-ID ordering, WRAP and INCR address rules, the 4 KB boundary, WLAST and response codes. Every puzzle states the AXI version it assumes.

    • 6topics
    • 6lessons

    Topics in this section

    1. 1The 4 KB Rule Splits a Burst1 lesson
    2. 2OKAY, SLVERR or DECERR?1 lesson
    3. 3WRAP Burst Address Sequence1 lesson
    4. 4WLAST One Beat Early1 lesson
    5. 5How Many Read Orders Are Legal?1 lesson
    6. 6Whose Data Is This? W Has No ID1 lesson

    About this puzzle set

    AXI4 channel independence, per-ID ordering, WRAP and INCR address rules, the 4 KB boundary, WLAST and response codes. Every puzzle states the AXI version it assumes.

    Puzzles in this topic

    Diagram
    1. The 4 KB Rule Splits a Burst  [Easy]
    2. OKAY, SLVERR or DECERR?  [Medium]
    3. WRAP Burst Address Sequence  [Medium]
    4. WLAST One Beat Early  [Medium]
    5. How Many Read Orders Are Legal?  [Medium]
    6. Whose Data Is This? W Has No ID  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    VLSI DV interview puzzle flow

    Diagram
    VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
    
    puzzle prompt
        |
        v
    requirements decode --> constraints/assumptions --> solve strategy
             |                          |                     |
             |                          v                     v
             +------------------> corner cases ---------> final answer
                                         |
                                         v
                                  explain trade-offs
    
    Use section visuals when available; fallback preserves reasoning flow.

    Related topics

    • Bus and Interface Protocol Puzzles section

    • VLSI DV Interview Puzzles hub

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    See also

    • Valid/Ready Handshake Puzzles
    • APB Protocol Puzzles
    • FIFO, Arbitration and Credit Puzzles