Stalls, dropped valids, unstable payloads, mutual-wait deadlocks, registered ready and skid buffers. Most interview misses come from reasoning about one cycle instead of the previous cycle's handshake state.
1. Counting Transfers in a Valid/Ready Trace [Easy]
2. Which Cycle Drops VALID Illegally? [Easy]
3. Payload Changes While Stalled [Easy]
4. Both Sides Wait: The Handshake Deadlock [Medium]
5. Registered READY Overflows a FIFO [Hard]
6. Register Slice: 50% Throughput Without Data Errors [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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v
requirements decode --> constraints/assumptions --> solve strategy
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+------------------> corner cases ---------> final answer
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explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.