Difficulty: Easy · Puzzle 3 of 6 · Topic: Valid/Ready Handshake Puzzles
Same rule family: while VALID is high and READY is low, the payload must hold its value. VALID is high for all 7 cycles. Find the violating cycle, list the beats the receiver actually gets, and say which intended beat is lost.
`timescale 1ns/1ns
module tb;
localparam int N = 7;
// cycle: 0123456
localparam bit [0:N-1] VALID = 7'b1111111;
localparam bit [0:N-1] READY = 7'b0010010;
localparam bit [27:0] DATA = {4'h3, 4'h3, 4'h3, 4'h7, 4'h9, 4'h9, 4'h2};
bit clk = 0;
int cyc = 0, bad = 0;
bit pv = 0, pr = 0;
bit [3:0] pd = 0;
always #5 clk = ~clk;
wire valid = VALID[cyc];
wire ready = READY[cyc];
wire [3:0] data = DATA[(N-1-cyc)*4 +: 4];
always @(posedge clk) begin
if (pv && !pr && valid && data !== pd) begin
bad++;
$display("VIOLATION cycle %0d: data changed 0x%0h -> 0x%0h while valid && !ready", cyc, pd, data);
end
if (valid && ready) $display("cycle %0d: transfer data=0x%0h", cyc, data);
pv <= valid; pr <= ready; pd <= data;
if (cyc == N-1) $display("violations = %0d", bad);
cyc <= cyc + 1;
end
initial #(10*N) $finish;
endmoduleCompare the data in each stalled cycle with the data in the cycle before it.
1) DATA by cycle: 3, 3, 3, 7, 9, 9, 2. READY is high only in cycles 2 and 5.
2) Cycles 0-1 stall with data 3 (stable). Cycle 2 transfers 3.
3) Cycle 3 offers a new beat, 7, and READY is low: stall.
4) Cycle 4 shows 9 while the previous cycle was a stall of 7 -> violation (data changed 7 -> 9). READY is still low.
5) Cycle 5 transfers 9. Cycle 6 shows 2 after a completed transfer, which is a fresh beat and legal.Answer: Violation in cycle 4 (7 changed to 9 while stalled). The receiver gets 3 in cycle 2 and 9 in cycle 5; the beat 7 is never delivered. The change to 2 in cycle 6 is legal.
Checked by running the code in Verilator 5; the printed output supports the answer above. Only the change that happens after a stall (cycle 4) is flagged; the beat 7 never transfers.
The data change at cycle 3 (3 -> 7) is NOT the violation: it follows the completed transfer in cycle 2, so it is a new beat. The violation is the change during the stall at cycle 4, and it silently loses a beat, so no protocol error appears at the receiver.
Does the stability rule cover only the data field? Model answer: No. Every payload and sideband signal qualified by VALID (data, LAST, strobes, ID, USER, address and control on a command channel) must be held while stalled. A LAST or USER bit that flips during a stall is the most common real violation because it is easy to forget.