Week 1

Day 1

SystemVerilog Language Puzzles

datatype-and-bit-puzzles-1: X-Bit Comparisons and Mixed Arithmetic (M); datatype-and-bit-puzzles-2: Signed vs Unsigned Comparison Trap (M); fork-join-puzzles-1: join vs join_any vs join_none (E); fork-join-puzzles-2: Loop Variable Capture in Detached Threads (M); fork-join-puzzles-3: wait fork Synchronization Point (E); queue-and-array-puzzles-1: Queue Mutation Plus Dynamic Resize (E); string-and-casting-puzzles-1: String Substr with Runtime Class Cast (E); string-and-casting-puzzles-4: Enum Safety with $cast (M)

Week 1

Day 2

OOP & Testbench Puzzles

handle-and-copy-puzzles-1: Shallow Copy in Nested Payload (E); handle-and-copy-puzzles-5: Handle Equality vs Content Equality (E); virtual-method-puzzles-1: Non-Virtual vs Virtual Through Base Handle (E); virtual-method-puzzles-2: Missing super.new with Required Base Args (E); parameterized-class-puzzles-1: Global Static vs Per-Specialization Static (E); parameterized-class-puzzles-2: Same Specialization via typedef Alias (M); factory-override-puzzles-1: Type Override vs Instance Override Precedence (M); factory-override-puzzles-6: Override Timing Relative to create Calls (E)

Week 1

Day 3

Concurrency & Timing Puzzles; Randomization & Constraint Puzzles

event-scheduling-puzzles-2: Does #0 Beat NBA? (E); event-scheduling-puzzles-5: Last NBA in a Process Wins (E); race-condition-puzzles-1: Competing Active Writers on x (M); race-condition-puzzles-3: Reading q Before the NBA (Not a Race) (E); clocking-block-puzzles-1: Why Every Sample Is One Cycle Old (M); clocking-block-puzzles-2: Interpreting |=> ##1 in Clocking Domain (E); semaphore-mailbox-puzzles-2: Bounded Mailbox put Deadlock (M); semaphore-mailbox-puzzles-3: try_get Busy Spin at Time 0 (E) | constraint-order-02-bidirectional-sum: Bidirectional Solving of x+y==10 (E); constraint-order-03-overlapping-if-else: if-else with Overlap on One Value (E); dist-02-range-cardinality-skew: Small Range with := vs Large Range with :/ (E); dist-06-zero-weight-value: Zero Weight Means Never Chosen (E); solve-before-01-classic-a-b: Classic a->b Bias Shift (E); solve-before-03-reverse-order-b-before-a: Reverse Bias with solve b before a (E); randomize-with-02-inline-if-else: Constraint Override by Name in a Derived Class (M); randomize-with-04-constraint-mode-toggle: constraint_mode Changes Pass/Fail (E)

Week 1

Day 4

SVA Assertion Puzzles

seq-001: Exact Delay Then Bounded Hold (M); imp-001: Overlap vs Non-Overlap (E); imp-002: Pure Vacuity (E); imp-006: OR Antecedent Trigger (E); temp-001: $past Startup History Hole (M); temp-003: $fell Is an Event, Not a Level (E); dbg-001: disable iff Reset Glitch Hides a Lost Grant (M); dbg-004: Overlapping Attempts Share One Grant (M)

Week 1

Day 5

Functional Coverage Puzzles

cov-cg-001: Auto vs explicit bins with illegal transition context (M); cov-cg-002: Default bin is not scored (E); cov-cross-001: Named cross bins that group tuples (M); cov-cross-002: Pure auto cross count (E); cov-opt-003: Instance coverage, type coverage and merge_instances (M); cov-opt-006: option.weight zero removes metric influence (E); cov-close-001: Sampling region off-by-one on state bins (M); cov-close-002: Unreachable bin from stimulus constraints (E)

Week 2

Day 6

Logic & Aptitude Puzzles; Scenario & Debug Puzzles

classic-01: 9 Balls, 1 Heavier, 2 Weighings (E); classic-02: 2 Eggs and 100 Floors (M); classic-04: Measure 4 Liters with 3L and 5L Jugs (E); probability-01: Biased Coin to Fair Bit (Von Neumann) (M); probability-03: Two Children, At Least One Boy (E); logic-01: Build XOR Using Only 2:1 MUXes (E); logic-02: One-Cycle Pulse Across Clock Domains (M); debug-06: Randomization Always Fails: Hidden Unsat (E) | tb-001: Handshake Hang: Missing item_done on One Branch (M); tb-002: Missing run_phase Objection in Test (E); dead-001: Early Return Leaves Objection Raised (E); dead-003: Semaphore Token Leak on Error Path (E); sb-001: Out-of-Order Responses Miscompared as Corruption (M); sb-002: Missing First Transaction After Reset (M); sb-003: Duplicate Transactions from Handle Reuse (E); round-001: Round: Mid-Test Reset Hangs the Regression (M)

Week 2

Day 7

UVM Testbench Puzzles

uvm-phase-01: Which Way Do the Phases Walk the Tree (E); uvm-phase-04: Derived build_phase Without super (E); uvm-config-01: Virtual Interface Set with a Relative Path from Top (E); uvm-config-04: Config Set Too Late for build_phase (E); uvm-seq-01: try_next_item Loop That Never Lets Time Pass (E); uvm-seq-05: Virtual Sequence Started With null (E); uvm-sb-01: Waiting Inside write() (E); uvm-sb-04: Desired, Mirrored and update() (E)

Week 2

Day 8

Clock, Reset & CDC Puzzles; Bus and Interface Protocol Puzzles

crc-rst-01: A Reset Pulse Between Two Clock Edges (E); crc-rst-02: The Counter Nobody Reset (E); crc-clk-01: AND Gate Fed Straight From a Flop (M); crc-clk-02: A Latch Makes the Gate Safe (E); crc-cdc-03: Why Gray Code Across Clock Domains (E); crc-cdc-06: Valid Crossed, Data Did Not (E); crc-ver-01: RTL Simulation Cannot Tell One Flop From Two (E); crc-ver-04: Three Muxes, One Unknown Select (E) | proto-hs-01: Counting Transfers in a Valid/Ready Trace (E); proto-hs-02: Which Cycle Drops VALID Illegally? (E); proto-hs-03: Payload Changes While Stalled (E); proto-apb-01: Setup, Access and Completed Transfers (E); proto-apb-02: Two Wait States: Total Cycles and Write Moment (E); proto-axi-01: The 4 KB Rule Splits a Burst (E); proto-axi-02: OKAY, SLVERR or DECERR? (M); proto-fifo-01: Sizing a FIFO for a Rate Mismatch Burst (E)

Week 2

Day 9

Interview prep

Framework; Testbench Hang; Constraint No-Solution; Vacuous Assertion Pass; Coverage Not Closing; Race That Only Shows on Silicon-Like Gate-Level Timing; Coverage Closed at 100 Percent but a Bug Escaped

Week 2

Day 10

Re-do and mock round

Cheatsheet; Interview-day tips; Re-do every puzzle scored 2 or lower; ask a friend to mutate one puzzle from each section.