Difficulty: Easy · Puzzle 6 of 6 · Topic: CDC Basics Puzzles
A source puts a word on a bus that changes every source clock (a live counter) and raises valid while the bus holds A3. Only valid is synchronised into the destination; when the destination sees valid it reads the bus. What does the destination read, and what fixes it?
`timescale 1ns/1ns
module tb;
reg clks = 0, clkd = 0;
always #5 clks = ~clks; // source period 10: posedges at 5, 15, 25, ...
always #12 clkd = ~clkd; // destination period 24: posedges at 12, 36, 60, 84, ...
reg [7:0] data = 8'hA0;
reg valid = 0;
always @(posedge clks) data <= data + 1; // the bus is a live counter, it moves every source cycle
reg v1 = 0, v2 = 0, v3 = 0;
always @(posedge clkd) begin
v1 <= valid; v2 <= v1; v3 <= v2; // only valid is synchronised
if (v2 && !v3) $display("t=%0d dst sees valid, bus=%h", $time, data);
end
initial begin
#26 $display("t=%0d src raises valid, bus=%h", $time, data);
valid = 1; // bus holds a3 from t=25 to t=35
#40 valid = 0; // valid stays up for 4 source cycles
#30 $finish;
end
endmoduleHow many source cycles pass before the destination sees valid?
1) The bus holds A3 from t=25 to t=35. valid is raised at t=26.
2) valid goes through two destination flops: the destination clock edge at t=36 gives v1, t=60 gives v2, and the edge at t=84 is the first at which v2 is high and v3 low.
3) At t=84 the destination reads the bus. By then the live counter has advanced from A3 to A8 (it moves at every source edge).
4) The word it reads (A8) is not the word that was valid (A3): the control crossed, the data did not.
5) Fix: hold the data in a register that does not change while the valid / handshake is in flight and read it only after the synchronised request, or use a FIFO, or a handshake.Answer: The destination reads A8, not A3, at t=84. Synchronising the control signal does not synchronise the data; the data must be held stable until the destination has used it (handshake, held register, or FIFO).
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: the destination reads a later word of the live bus than the one that was valid.
Thinking a synchronised valid makes the data 'valid' on the other side. The data is not held for the several cycles the control needs to cross; even though no bit is metastable, it is a different word. The same problem exists when two related signals each cross through their own two-flop synchroniser.
What changes if the destination clock were much faster than the source clock? Model answer: the data would still have advanced by the delay of the synchroniser, which is a fixed number of destination cycles, so with a faster destination it could be fewer source cycles; but nothing guarantees it, so the same fix is required.