A clock is a signal like any other until you gate or switch it. These puzzles are about the pulses a gate can create: truncated pulses, runt pulses, extra edges, and the structures (latch-based gating, safe clock switching) that prevent them.
1. AND Gate Fed Straight From a Flop [Medium]
2. A Latch Makes the Gate Safe [Easy]
3. Which Gate Wants Which Phase? [Medium]
4. Switching a Clock Mux With the Select [Medium]
5. The Glitch-Free Clock Switch [Hard]
6. Does the Gated Flop See the Old Data? [Medium]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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requirements decode --> constraints/assumptions --> solve strategy
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+------------------> corner cases ---------> final answer
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explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.