Difficulty: Medium · Puzzle 3 of 6 · Topic: Clock Gating & Clock Mux Puzzles
Two gating cells see the same clock. The AND gate has en go from 0 to 1 and the OR gate has dis go from 0 to 1 (clock disabled), both at t=12 while clk is low. List every rising edge each output produces.
`timescale 1ns/1ns
module tb;
reg clk = 0, en = 0, dis = 0;
always #5 clk = ~clk; // high 5..10, 15..20, 25..30; low 10..15, 20..25
wire g_and = clk & en; // en=0 holds the output low
wire g_or = clk | dis; // dis=1 holds the output high
always @(posedge g_and) $display("t=%0d AND-gate rising edge", $time);
always @(posedge g_or) $display("t=%0d OR-gate rising edge", $time);
initial begin
#12 en = 1; dis = 1; // both controls change at t=12, while clk is low
#21 $finish;
end
endmoduleThe OR gate output follows clk until dis is 1; then it is held high.
1) The AND output is 0 while en=0, so no rising edge is produced at t=5. en rises at t=12 while clk is low, so nothing happens at the output; the rising edges at t=15 and t=25 pass through. The AND cell is being switched in its safe phase (clk low).
2) The OR output equals clk while dis=0, so it rises at t=5.
3) dis rises at t=12, clk is low, so the OR output (clk | dis) goes from 0 to 1 at t=12: a rising edge that is not a clock edge.
4) After that the OR output stays high, so there are no more edges: the gate is disabled, but at the cost of one spurious edge.
5) Rule: an AND-type gate may change its enable only while clk is low; an OR-type gate (holds the clock high when disabled) may change only while clk is high.Answer: OR gate rising edges at t=5 and t=12 (the second is a spurious edge), AND gate rising edges at t=15 and t=25. Each gate's control may only change in its own safe phase: low clock for AND, high clock for OR.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: the OR gate produces a rising edge at t=12 when its control changes during the low phase; the AND gate is clean.
Memorising 'enable changes when the clock is low' for every gate. That is only for the AND type; the OR type (parks the clock high) needs the opposite phase, and changing it while the clock is low creates a rising edge.
For the OR gate, which latch phase gives a safe disable? Model answer: a latch that is transparent while clk is high (the disable is frozen during the low phase), so dis can only change while the OR gate output is held high by clk.