Difficulty: Easy · Puzzle 2 of 6 · Topic: Clock Gating & Clock Mux Puzzles
The same enable flop and command as before, but the enable goes through a latch that is transparent while clk is low before the AND gate. List the high pulses of gclk with their widths.
`timescale 1ns/1ns
module tb;
reg clk = 0, en_cmd = 0, en = 0;
reg en_l = 0;
always #5 clk = ~clk; // posedges at 5, 15, 25, 35, 45
always @(posedge clk) en <= #1 en_cmd; // same enable flop (1 ns clock-to-q) as before
always @(*) if (!clk) en_l = en; // latch, transparent while clk is low
wire gclk = clk & en_l;
integer t_r = -1;
always @(gclk)
if (gclk) t_r = $time;
else if (t_r >= 0) $display("gclk high %0d..%0d width=%0d", t_r, $time, $time - t_r);
initial begin
#12 en_cmd = 1;
#20 en_cmd = 0; // t=32
#18 $finish;
end
endmoduleWhile clk is high the latch holds the value it had when clk rose.
1) The latch passes en only while clk is low and holds it while clk is high, so the AND gate sees an enable that is stable for the whole high phase.
2) en rises at t=16 (clk high): the latch is closed and keeps 0 until clk falls at t=20, when it passes 1. The edge at t=15 is therefore skipped completely, there is no pulse at 16.
3) The first full pulse is the edge at t=25: 25..30.
4) The command falls at t=32; en falls at t=36 (clk is high at 35..40) and the latch holds 1 until t=40, so the pulse at 35 is also a full 35..40.
5) The latch passes 0 at t=40, so the next edge at 45 is not produced.Answer: gclk high 25..30 (width 5) and 35..40 (width 5). Only complete pulses appear: the enable change is deferred to the next low phase, so the edge at t=15 is skipped and the edge at t=35 is completed.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: with the low-transparent latch every pulse is full width; the enable change is taken at the next edge.
Assuming the enable takes effect on the very next edge. With a latch (or any proper integrated clock-gating cell) a change near an edge takes effect one edge later, never mid-pulse. Count one cycle of enable latency in your checks, and also note the gate is only safe if the enable settles before the clock rises (the gating check).
Why must the latch be transparent while clk is LOW for an AND gate? Model answer: the AND gate only matters while clk is high, so the enable must be frozen during the high phase and may change only when clk is low; a latch transparent-high would pass changes straight into the gate during the high phase and glitch it.