Difficulty: Medium · Puzzle 4 of 6 · Topic: Clock Gating & Clock Mux Puzzles
clk_o = sel ? clkb : clka, with clka (period 10, high 5 ns) and clkb (period 6, high 3 ns). sel changes from 0 to 1 at t=7 when clka is high and clkb is low. List the high pulses of clk_o and say whether any is illegal.
`timescale 1ns/1ns
module tb;
reg clka = 0, clkb = 0, sel = 0;
always #5 clka = ~clka; // period 10, high 5..10, 15..20
always #3 clkb = ~clkb; // period 6, rises at 3, 9, 15; high for 3 ns each time
wire clk_o = sel ? clkb : clka;
integer t_r = -1;
always @(clk_o)
if (clk_o) t_r = $time;
else if (t_r >= 0) $display("clk_o high %0d..%0d width=%0d", t_r, $time, $time - t_r);
initial begin
#7 sel = 1; // switch while clka is high and clkb is low
#12 $finish;
end
endmoduleAt t=7 the mux output was following clka (high) and starts following clkb (low).
1) clka rises at t=5, so clk_o rises at t=5.
2) At t=7 sel switches. clka is high, clkb is low, so clk_o drops from 1 to 0 at t=7: the pulse is only 2 ns wide instead of 5.
3) clk_o then follows clkb: clkb rises at 9 and falls at 12, a normal 3 ns pulse; the next one is 15..18.
4) The 2 ns pulse is a runt: shorter than the minimum pulse width of even the faster clock (3 ns), so it is illegal.Answer: Pulses: 5..7 (width 2), 9..12 (width 3), 15..18 (width 3). The first is an illegal runt: it is below the minimum pulse width (3 ns), created because sel changed while the two clocks were in different states.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: a 2 ns runt pulse appears at the switch.
Calling this 'just a glitch in simulation'. The same pulse exists in silicon as a runt that can clock flops unreliably or leave them metastable, and zero-delay RTL shows it exactly as it would be, so a bench that checks minimum pulse width after every sel change catches it.
Would the result be safe if sel switched at t=11, when both clocks happen to be low? Model answer: yes for that one instant only (the output is low before and after and the next edge comes from clkb), but it is luck of phase, not a design: the select can change at any phase, so a safe switch needs the proper handshake structure.