Difficulty: Medium · Puzzle 1 of 6 · Topic: Clock Gating & Clock Mux Puzzles
An enable flop (clock-to-q 1 ns) drives an AND gate with the clock directly: gclk = clk & en. The enable command is 1 from t=12 to t=32. List the high pulses of gclk with their widths. Which of them are illegal for a flop clocked by gclk?
`timescale 1ns/1ns
module tb;
reg clk = 0, en_cmd = 0, en = 0;
always #5 clk = ~clk; // posedges at 5, 15, 25, 35
always @(posedge clk) en <= #1 en_cmd; // enable flop with 1 ns clock-to-q, feeding the AND gate directly
wire gclk = clk & en;
integer t_r = -1;
always @(gclk)
if (gclk) t_r = $time;
else if (t_r >= 0) $display("gclk high %0d..%0d width=%0d", t_r, $time, $time - t_r);
initial begin
#12 en_cmd = 1;
#20 en_cmd = 0; // t=32
#8 $finish;
end
endmoduleThe enable changes 1 ns after a rising clock edge, while the clock is still high.
1) The enable flop samples the command at each clk edge and updates 1 ns later.
2) At the edge at t=15 the command is 1: en rises at t=16 while clk is high, so gclk rises at t=16 and falls with clk at t=20: a 4 ns pulse instead of 5.
3) At t=25 en is already 1, so the pulse is the full 25..30, 5 ns.
4) The command falls at t=32. At the edge at t=35 en is still 1 (it falls 1 ns later), so gclk rises at 35; en falls at 36 and cuts gclk low: a 1 ns pulse.
5) The 4 ns pulse (truncated, late rising edge) and the 1 ns pulse (a runt) are glitches: the gate output changed while clk was high. The 1 ns pulse is the worst: it may or may not clock the flop reliably.Answer: gclk high 16..20 (width 4), 25..30 (width 5), 35..36 (width 1). The first and last are illegal: the enable changed while clk was high, truncating the first pulse and creating a 1 ns runt on the last.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: with a 1 ns clock-to-q on the enable, the gate output is truncated at the start and has a 1 ns runt at the end.
Believing a gate fed from a posedge flop is safe because the flop is synchronous. The enable can only change safely while the clock is low (for an AND gate); a posedge-launched enable changes just after the rising edge, so the gate output is cut or created mid-pulse. In zero-delay RTL (no clock-to-q) the glitch is invisible, so it passes simulation.
What would the pulse list look like in zero-delay RTL with en <= en_cmd (no #1)? Model answer: gclk would show clean full-width pulses (rising at the same time as clk, one delta later), so RTL simulation passes while the real circuit glitches.