Simulation is the weakest tool for clock-domain and reset bugs: it is zero-delay, 4-state, and usually driven by clean clocks. These puzzles are about what a bench cannot see, how to make it see more, and the traps in the checks themselves.
1. RTL Simulation Cannot Tell One Flop From Two [Easy]
2. Clock Ratios That Hide Phase Bugs [Medium]
3. A Reset Checker That Never Fires [Medium]
4. Three Muxes, One Unknown Select [Easy]
5. Gate-Level Skew Shoots Data Through [Hard]
6. Reset Ordering Assertion: Same Edge or Strictly Later? [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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requirements decode --> constraints/assumptions --> solve strategy
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+------------------> corner cases ---------> final answer
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explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.