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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
    • Reset Puzzles
    • Clock Gating & Clock Mux Puzzles
    • CDC Basics Puzzles
    • Verifying CDC & Reset Puzzles
      • RTL Simulation Cannot Tell One Flop From Two
      • Clock Ratios That Hide Phase Bugs
      • A Reset Checker That Never Fires
      • Three Muxes, One Unknown Select
      • Gate-Level Skew Shoots Data Through
      • Reset Ordering Assertion: Same Edge or Strictly Later?
    • Clock, Reset & CDC Puzzles: Tricky Q&A
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Verifying CDC & Reset Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Clock, Reset & CDC Puzzles
  4. Verifying CDC & Reset Puzzles
  5. Three Muxes, One Unknown Select
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    VLSI DV Interview PuzzlesAll levels

    Three Muxes, One Unknown Select

    The select s is X. The same 2:1 multiplexer is written three ways: the conditional operator, if/else, and an AND-OR expression. Predict the printed outputs for (a=1, b=0) and for (a=1, b=1). Which style hides an unknown select, and which one reports X when the answer is certain?

    Puzzle

    Difficulty: Easy · Puzzle 4 of 6 · Topic: Verifying CDC & Reset Puzzles

    The select s is X. The same 2:1 multiplexer is written three ways: the conditional operator, if/else, and an AND-OR expression. Predict the printed outputs for (a=1, b=0) and for (a=1, b=1). Which style hides an unknown select, and which one reports X when the answer is certain?

    Code

    tb.sv
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    `timescale 1ns/1ns
    module tb;
      reg s = 1'bx;
      reg a, b;
      wire y_tern = s ? a : b;                    // conditional operator
      reg y_if;
      always_comb if (s) y_if = a; else y_if = b; // if/else
      wire y_andor = (s & a) | (~s & b);          // gate-level style AND-OR mux
      initial begin
        a = 1; b = 0; #1;
        $display("a=%b b=%b  tern=%b if=%b andor=%b", a, b, y_tern, y_if, y_andor);
        a = 1; b = 1; #1;
        $display("a=%b b=%b  tern=%b if=%b andor=%b", a, b, y_tern, y_if, y_andor);
        #1 $finish;
      end
    endmodule

    Hint

    if (X) takes the else branch; the conditional operator merges the two inputs bit by bit.

    Step-by-step solution

    Diagram
    1) Conditional operator with s = X: bits where a and b agree keep their value, bits that differ become X. For (1, 0): X. For (1, 1): 1.
    2) if/else: an X condition counts as false, so the else branch is always taken: y = b. For (1, 0): 0; for (1, 1): 1. It hides the unknown select (X-optimism).
    3) AND-OR: (s & a) | (~s & b) with s = X: for (1, 0) it is X | 0 = X; for (1, 1) it is X | X = X, even though both inputs are 1 and the answer is certain (X-pessimism).
    4) So the three styles disagree on identical hardware: the choice of coding style changes what RTL simulation reports about unknowns.

    Answer

    Answer: a=1 b=0: tern=x if=0 andor=x. a=1 b=1: tern=1 if=1 andor=x. The if/else is optimistic (hides the X select), the AND-OR is pessimistic (X although both inputs are 1), the conditional operator is the accurate one.

    How this was checked

    Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus (4-state): the three coding styles give three different answers for an X select.

    Why candidates get it wrong

    Trusting the first X (or the absence of one). if/else can hide an X that gate-level simulation will later show, and AND-OR forms can create an X that is not real. When an X appears, decide whether it is real or pessimism before debugging the wrong thing.

    Interviewer follow-up

    Which style is best for finding an uninitialised select in RTL? Model answer: the conditional operator (or an explicit check of the select with !==), since it propagates an X select to the output when the two inputs differ, instead of hiding it as if/else does.

    Related topics

    • Back to Verifying CDC & Reset Puzzles

    • Clock, Reset & CDC Puzzles section

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    See also

    • RTL Simulation Cannot Tell One Flop From Two
    • Clock Ratios That Hide Phase Bugs
    • Reset Ordering Assertion: Same Edge or Strictly Later?