Difficulty: Easy · Puzzle 1 of 6 · Topic: Verifying CDC & Reset Puzzles
A flag crosses from a 10 ns clock to a 14 ns clock once through a bare single flop and once through a two-flop synchroniser. List the changes of both outputs. Can this simulation prove that the single-flop version is a bug?
`timescale 1ns/1ns
module tb;
reg clks = 0, clkd = 0;
always #5 clks = ~clks; // source period 10
always #7 clkd = ~clkd; // destination period 14: posedges at 7, 21, 35, 49, ...
reg flag = 0;
always @(posedge clks) if ($time >= 20) flag <= 1; // flag rises after the source edge at t=25
reg one_ff, two_a, two_b;
always @(posedge clkd) one_ff <= flag; // bare single flop
always @(posedge clkd) begin two_a <= flag; two_b <= two_a; end // two-flop synchroniser
always @(one_ff) $display("t=%0d one-flop out=%b", $time, one_ff);
always @(two_b) $display("t=%0d two-flop out=%b", $time, two_b);
initial begin
#60 $finish;
end
endmoduleNeither flop can go metastable in RTL.
1) The flag rises after the source edge at t=25.
2) The destination edges are at 7, 21, 35, 49: the first edge after 25 is t=35, at which the single flop captures 1: one-flop out rises at t=35.
3) The two-flop version loads the first stage at t=35 and the second at t=49: it rises at t=49, one destination cycle later.
4) Both outputs are clean, with no X or glitch: the simulator resolves each capture to the old or the new value, never to an unstable one.
5) So the simulation shows only a one-cycle latency difference; it cannot show the failure (metastability) that makes the single flop a bug. That needs structural CDC analysis, an MTBF model or gate-level / SDF checks.Answer: One-flop out rises at t=35, two-flop out at t=49. Both are clean, so RTL simulation passes both designs and cannot reveal that the single-flop crossing is unsafe. Use a CDC tool (structural check) and MTBF analysis.
Checked by running the code in Icarus Verilog 13; the printed output supports the answer above. Icarus: both crossings behave logically; the only difference is one extra destination cycle of latency. Metastability is not simulated.
Reading a clean waveform as evidence of a safe crossing. A passing RTL simulation says nothing about metastability, because capture is idealised; the only RTL difference is latency, which is also why a pure latency check in a scoreboard cannot catch a missing synchroniser.
Name one simulation technique that does try to expose CDC problems. Model answer: CDC-aware simulation that randomly delays or randomises the bit that is captured near the edge (metastability injection) in synchroniser cells, together with randomised clock phases and periods; it still complements, not replaces, static CDC analysis.