Interview puzzles on the things that break chips after simulation passes: asynchronous and synchronous reset behaviour, reset ordering, clock gating and clock muxes, synchronisers and multi-bit crossings, and how a verification engineer actually catches a CDC or reset bug. Every puzzle has one defensible answer under stated assumptions and a machine check.
Reset Puzzles — 6 puzzles
Clock Gating & Clock Mux Puzzles — 6 puzzles
CDC Basics Puzzles — 6 puzzles
Verifying CDC & Reset Puzzles — 6 puzzlesOpen each topic and attempt every puzzle cold, writing your predicted answer first.
Only then read the step-by-step solution and confirm the exact answer.
Re-read the 'why candidates get it wrong' note — that is the actual interview signal.
Finish with the section Q&A to rehearse explaining the rule out loud.