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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
    • UVM Phases and Objections
    • Factory and config_db
    • Sequences and Sequencers
    • Analysis, Scoreboards and RAL
    • UVM Testbench Puzzles: Tricky Q&A
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←UVM Testbench Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. UVM Testbench Puzzles
  4. UVM Testbench Puzzles: Tricky Q&A
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    VLSI DV Interview PuzzlesAll levels

    UVM Testbench Puzzles: Tricky Q&A

    Rapid-fire interview Q&A for UVM Testbench Puzzles.

    Section Q&A

    Rapid-fire questions an interviewer asks around UVM Testbench Puzzles. Answer out loud, then check yourself.

    Q1. A parent and a child both set the same config_db field for the child. Who wins, and how do you let a test override an env default?

    Answer: The set made from the context higher in the hierarchy wins, whatever the timing; only between sets of the same level does the later write win. So the env should not hard-set a value the test may want to change: let the env only get with a default, and the test sets.

    Trap: Saying 'the last set wins' or 'the most specific pattern wins'.

    Q2. get() on uvm_config_db returns 0 although the field name and path are right. Name the quick checks.

    Answer: Check in order: the type parameter equals the type used in set (a base set is not found by a derived get, int is not bit [31:0]); the path includes the real full name (uvm_test_top.... for a null context); the set ran before the get (the reader's phase has not passed); and the context argument of get plus its instance string.

    Trap: Assuming the object's dynamic type is used for lookup.

    Q3. Why can a UVM test appear to pass with the sequence barely running?

    Answer: Because nothing holds a run-phase objection while it runs: a default sequence, a sequence started with no raise, or an objection dropped early ends the phase and kills the threads. Make the owner of the activity raise and drop (for example set_automatic_phase_objection in UVM 1.2) and check in the log that the expected number of items passed.

    Trap: Treating 'no errors' as success when zero transactions were compared.

    Q4. In what order do the phases walk the tree, and what does that decide?

    Answer: build and final go parents first; connect, end_of_elaboration, start_of_simulation, extract, check and report go children first; run is concurrent. So a parent can create and configure its children in build, and a parent can rely on its children's connections being done in connect; verdicts belong in check/report, not earlier.

    Trap: Believing create() runs the child's build_phase immediately.

    Q5. How do you verify a register model really tracks the DUT?

    Answer: Decide how the mirror is predicted (auto-predict only if the model is the sole master, otherwise an explicit predictor on a monitor that sees all traffic), then use front-door reads with mirror(UVM_CHECK) and use backdoor access only for setup and peeks, remembering that volatile and clear-on-read registers need front-door or directed checks.

    Trap: Leaving the default (no auto-predict, no predictor) and then trusting mirror checks.

    Q6. A scoreboard receives two analysis streams in one class; what are the options?

    Answer: Use uvm_analysis_imp_decl to get separate write_exp/write_act methods, or use two uvm_tlm_analysis_fifos and read them in run_phase. Keep write() non-blocking; do the clocked compare in a task that pulls from the FIFOs.

    Trap: Two imps of the same type calling one write(), or timing controls inside write().

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    See also

    • UVM Phases and Objections
    • Factory and config_db
    • Sequences and Sequencers