Scoreboard and register-model questions are about wiring and bookkeeping: which function receives which stream, which value the model holds and which accesses reach the DUT. The puzzles use UVM 1.2 behaviour.
1. Waiting Inside write() [Easy]
2. Two Analysis Imps, One write() [Medium]
3. Auto-Predict, No Predictor, and a Second Master [Hard]
4. Desired, Mirrored and update() [Easy]
5. Backdoor Read of a Clear-on-Read Register [Medium]
6. Register Reads Return Zero With a Good Waveform [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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v
requirements decode --> constraints/assumptions --> solve strategy
| | |
| v v
+------------------> corner cases ---------> final answer
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v
explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.