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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
    • UVM Phases and Objections
    • Factory and config_db
    • Sequences and Sequencers
      • try_next_item Loop That Never Lets Time Pass
      • When finish_item Returns
      • lock Versus grab Ordering
      • Inline Constraint That Constrains Nothing
      • Virtual Sequence Started With null
      • Default Sequence Ends at Time Zero
    • Analysis, Scoreboards and RAL
    • UVM Testbench Puzzles: Tricky Q&A
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Sequences and Sequencers
  1. Topics
  2. DV Interview Puzzles
  3. UVM Testbench Puzzles
  4. Sequences and Sequencers
  5. Default Sequence Ends at Time Zero
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    VLSI DV Interview PuzzlesAll levels

    Default Sequence Ends at Time Zero

    UVM 1.2. A default sequence is configured on the agent's sequencer for run_phase, and the test's run_phase is empty (no objection). The traffic sequence just does `uvm_do` ten items. How long does the simulation run, and what are two fixes?

    Puzzle

    Difficulty: Hard · Puzzle 6 of 6 · Topic: Sequences and Sequencers

    UVM 1.2. A default sequence is configured on the agent's sequencer for run_phase, and the test's run_phase is empty (no objection). The traffic sequence just does `uvm_do` ten items. How long does the simulation run, and what are two fixes?

    Code

    design.sv
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    // env build_phase
    uvm_config_db#(uvm_object_wrapper)::set(this, "agent.sqr.run_phase",
                                            "default_sequence", traffic_seq::get_type());
    
    class traffic_seq extends uvm_sequence #(bus_item);
      `uvm_object_utils(traffic_seq)
      function new(string name = "traffic_seq"); super.new(name); endfunction
      task body();
        repeat (10) `uvm_do(req)
      endtask
    endclass

    Hint

    Starting a sequence is not the same as holding the phase open. Who owns the objection here?

    Step-by-step solution

    Diagram
    1) The sequencer starts the default sequence at the beginning of run_phase, but starting it does not by itself raise an objection.
    2) No component holds an objection (the test's run_phase is empty), so the run phase ends at once; the sequence thread is killed with the phase and the simulation ends at time 0 (at most the first item has been offered).
    3) Fix 1 (UVM 1.2): call `set_automatic_phase_objection(1)` in the sequence's constructor, so the sequence raises and drops an objection on the phase it is started in for the duration of body().
    4) Fix 2 (works in any version): in the sequence body use `get_starting_phase().raise_objection(this)` and drop it at the end (before 1.2 this was the `starting_phase` member).

    Answer

    Answer: It ends at time 0: nothing holds an objection. Fix with set_automatic_phase_objection(1) in the sequence constructor (UVM 1.2) or by raising/dropping on the starting phase in the sequence body.

    How this was checked

    Not run here: The UVM library is not installed here, so this cannot be executed; default_sequence start-up and set_automatic_phase_objection are UVM 1.2 library behaviour.. The answer follows the language rules and the solution steps above.

    Why candidates get it wrong

    Version: UVM 1.1d needed the manual raise/drop on `starting_phase`; in 1.2 `starting_phase` is deprecated in favour of get_starting_phase()/set_automatic_phase_objection; a recipe copied from a 1.1d example still runs but may warn.

    Interviewer follow-up

    With automatic phase objection on, what ends the objection if body() hangs? Model answer: nothing; the objection is dropped only when body() returns, so a sequence that blocks forever keeps the phase open until the global timeout, which is why such sequences still need a bounded body or a timeout.

    Related topics

    • Back to Sequences and Sequencers

    • UVM Testbench Puzzles section

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    See also

    • try_next_item Loop That Never Lets Time Pass
    • When finish_item Returns
    • lock Versus grab Ordering