Interviewers use phase questions to check that you know the direction each phase walks the tree, who holds the simulation open and why an apparently correct component silently does nothing. The puzzles here use UVM 1.2 and focus on ordering across components, drain time, objection extension and creation rules rather than on definitions.
1. Which Way Do the Phases Walk the Tree [Easy]
2. Drain Time After the Last Drop [Medium]
3. PASSED Banner Printed Before the Error [Medium]
4. Derived build_phase Without super [Easy]
5. phase_ready_to_end Never Extends [Hard]
6. Creating a Component After Build [Medium]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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v
requirements decode --> constraints/assumptions --> solve strategy
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| v v
+------------------> corner cases ---------> final answer
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v
explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.