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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
    • UVM Phases and Objections
      • Which Way Do the Phases Walk the Tree
      • Drain Time After the Last Drop
      • PASSED Banner Printed Before the Error
      • Derived build_phase Without super
      • phase_ready_to_end Never Extends
      • Creating a Component After Build
    • Factory and config_db
    • Sequences and Sequencers
    • Analysis, Scoreboards and RAL
    • UVM Testbench Puzzles: Tricky Q&A
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←UVM Phases and Objections
  1. Topics
  2. DV Interview Puzzles
  3. UVM Testbench Puzzles
  4. UVM Phases and Objections
  5. Which Way Do the Phases Walk the Tree
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    VLSI DV Interview PuzzlesAll levels

    Which Way Do the Phases Walk the Tree

    UVM 1.2. The hierarchy is uvm_test_top -> env -> agent -> drv (each created by its parent in build_phase). Every component derives from the logger below. Give the order of component names printed for build_phase, connect_phase, report_phase and final_phase.

    Puzzle

    Difficulty: Easy · Puzzle 1 of 6 · Topic: UVM Phases and Objections

    UVM 1.2. The hierarchy is uvm_test_top -> env -> agent -> drv (each created by its parent in build_phase). Every component derives from the logger below. Give the order of component names printed for build_phase, connect_phase, report_phase and final_phase.

    Code

    design.sv
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    class phase_logger extends uvm_component;
      function new(string name, uvm_component parent);
        super.new(name, parent);
      endfunction
      function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        `uvm_info("PH", $sformatf("build %s", get_name()), UVM_LOW)
      endfunction
      function void connect_phase(uvm_phase phase);
        `uvm_info("PH", $sformatf("connect %s", get_name()), UVM_LOW)
      endfunction
      function void report_phase(uvm_phase phase);
        `uvm_info("PH", $sformatf("report %s", get_name()), UVM_LOW)
      endfunction
      function void final_phase(uvm_phase phase);
        `uvm_info("PH", $sformatf("final %s", get_name()), UVM_LOW)
      endfunction
    endclass

    Hint

    Two of the four phases walk top-down and two walk bottom-up. Think about why build must be one of the top-down ones.

    Step-by-step solution

    Diagram
    1) build_phase is top-down: a parent's build_phase must run first because that is where it creates its children. Order: uvm_test_top, env, agent, drv.
    2) connect_phase is bottom-up (children before parents), so by the time a parent connects, its children's own internal connections are already made. Order: drv, agent, env, uvm_test_top.
    3) report_phase is bottom-up like the other function phases of the post-run group (extract, check, report): drv, agent, env, uvm_test_top.
    4) final_phase is top-down: uvm_test_top, env, agent, drv.

    Answer

    Answer: build: test, env, agent, drv. connect: drv, agent, env, test. report: drv, agent, env, test. final: test, env, agent, drv.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. Hand-written model of the documented UVM 1.2 behaviour in plain SystemVerilog (Verilator), not the UVM library: each phase walks a chain of four components top-down (parent first) or bottom-up (children first); the tree is prebuilt here, whereas UVM creates children inside the parent's build_phase.

    Why candidates get it wrong

    Siblings are not ordered by creation: within one level the traversal follows the parent's child list (sorted by instance name), so never rely on one sibling's build or connect having run before another's.

    Interviewer follow-up

    Why can a parent's connect_phase safely call `agent.mon.ap.connect(sb.exp_imp)` while a parent's build_phase can not safely use `agent.mon`? Model answer: connect_phase is bottom-up, so the agent and monitor have already finished build AND their own connect before the env connects across them; build_phase is top-down, so when env.build_phase runs the agent has only just been created by it (or not at all) and its own build_phase has not run yet.

    Related topics

    • Back to UVM Phases and Objections

    • UVM Testbench Puzzles section

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    See also

    • PASSED Banner Printed Before the Error
    • Derived build_phase Without super
    • phase_ready_to_end Never Extends