Difficulty: Medium · Puzzle 6 of 6 · Topic: UVM Phases and Objections
UVM 1.2. To save effort the test creates an optional checker only when a plusarg is present, and does it in connect_phase (after reading the plusarg there). What happens at run time when the plusarg is given?
class my_test extends uvm_test;
`uvm_component_utils(my_test)
my_env env;
late_checker chk;
function new(string name, uvm_component parent); super.new(name, parent); endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = my_env::type_id::create("env", this);
endfunction
function void connect_phase(uvm_phase phase);
if ($test$plusargs("WITH_CHK")) begin
chk = late_checker::type_id::create("chk", this);
env.agent.mon.ap.connect(chk.analysis_export);
end
endfunction
endclassComponents can only exist before a certain phase has finished. Which one, and what does the library do if you break the rule?
1) All components must be created during build_phase (or before it, from the build of an ancestor); after the build phase has ended UVM no longer runs build_phase for newcomers, so creation is refused.
2) In UVM 1.2 the component constructor reports a UVM_FATAL (id ILLCRT) saying that creating a component after the build phase has ended is illegal. The simulation stops there.
3) Fix: create the checker in build_phase under the same plusarg test (conditional creation in build_phase is fine), and connect it in connect_phase if it is non-null.Answer: A UVM_FATAL (ILLCRT) at the create call in connect_phase; fix by creating the optional component in build_phase and connecting it later.
Not run here: The UVM library is not installed here, so this cannot be executed; the ILLCRT fatal is raised inside the UVM component constructor; there is nothing meaningful to emulate in plain SystemVerilog.. The answer follows the language rules and the solution steps above.
Conditional creation is legal, late creation is not: the condition can stay, only the phase in which the create call runs must move to build_phase.
Which two kinds of object are not bound by this rule, and why? Model answer: uvm_objects (sequences, items, config objects) can be created in any phase, since they have no phase scheduling or hierarchy; only uvm_components need a build_phase, a parent and a place in the tree before the build phase ends.