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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
    • UVM Phases and Objections
      • Which Way Do the Phases Walk the Tree
      • Drain Time After the Last Drop
      • PASSED Banner Printed Before the Error
      • Derived build_phase Without super
      • phase_ready_to_end Never Extends
      • Creating a Component After Build
    • Factory and config_db
    • Sequences and Sequencers
    • Analysis, Scoreboards and RAL
    • UVM Testbench Puzzles: Tricky Q&A
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←UVM Phases and Objections
  1. Topics
  2. DV Interview Puzzles
  3. UVM Testbench Puzzles
  4. UVM Phases and Objections
  5. phase_ready_to_end Never Extends
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    VLSI DV Interview PuzzlesAll levels

    phase_ready_to_end Never Extends

    UVM 1.2. The DUT answers up to 200 ns after the last request. The scoreboard tries to keep the run phase open until its pending queue is empty by using phase_ready_to_end, but the run still ends with 'pending at end' errors. Find the defect.

    Puzzle

    Difficulty: Hard · Puzzle 5 of 6 · Topic: UVM Phases and Objections

    UVM 1.2. The DUT answers up to 200 ns after the last request. The scoreboard tries to keep the run phase open until its pending queue is empty by using phase_ready_to_end, but the run still ends with 'pending at end' errors. Find the defect.

    Code

    design.sv
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    class my_sb extends uvm_scoreboard;
      `uvm_component_utils(my_sb)
      txn pending[$];
      function new(string name, uvm_component parent); super.new(name, parent); endfunction
      function void phase_ready_to_end(uvm_phase phase);
        if (phase.get_name() != "run_phase") return;
        if (pending.size() > 0) begin
          phase.raise_objection(this, "draining scoreboard");
          fork begin
            wait (pending.size() == 0);
            phase.drop_objection(this);
          end join_none
        end
      endfunction
      function void check_phase(uvm_phase phase);
        if (pending.size() > 0) `uvm_error("SB", "pending at end")
      endfunction
    endclass

    Hint

    The mechanism (raise inside the callback, drop later from a forked process) is fine. Look at the very first line of the callback.

    Step-by-step solution

    Diagram
    1) UVM calls phase_ready_to_end on every component when a phase's objection count reaches zero (after the drain time), for run and for each runtime sub-phase that uses objections.
    2) Built-in phase names do not carry the `_phase` suffix: the run phase's `get_name()` is "run".
    3) The guard compares with "run_phase", is always true, and the callback returns immediately, so the objection is never raised and the phase ends with items still pending.
    4) Fix: compare with "run" (or compare `phase.get_imp()` with `uvm_run_phase::get()`). The fork/join_none is required because the callback is a function and cannot block.

    Answer

    Answer: The guard `phase.get_name() != "run_phase"` is always true because the phase name is "run"; the callback returns early, never raises the objection.

    How this was checked

    Not run here: The UVM library is not installed here, so this cannot be executed; phase_ready_to_end, phase names and the objection machinery are UVM library internals; no plain-SV stand-in could show the name-mismatch honestly.. The answer follows the language rules and the solution steps above.

    Why candidates get it wrong

    Phase names drop the suffix ("run", "build", "main"), so a name test written with `_phase` silently never matches and you get no warning, just a callback that does nothing.

    Interviewer follow-up

    Why is the guard needed at all, and what extra problem does an unguarded callback cause? Model answer: the callback is invoked for every objection-using phase of every component, not just run; unguarded, the scoreboard would also raise objections in the runtime sub-phases (main, shutdown, ...) when pending is non-empty at those boundaries, holding phases open for a condition that only means something at the end of the run.

    Related topics

    • Back to UVM Phases and Objections

    • UVM Testbench Puzzles section

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    See also

    • Which Way Do the Phases Walk the Tree
    • Drain Time After the Last Drop
    • PASSED Banner Printed Before the Error