Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
    • UVM Phases and Objections
      • Which Way Do the Phases Walk the Tree
      • Drain Time After the Last Drop
      • PASSED Banner Printed Before the Error
      • Derived build_phase Without super
      • phase_ready_to_end Never Extends
      • Creating a Component After Build
    • Factory and config_db
    • Sequences and Sequencers
    • Analysis, Scoreboards and RAL
    • UVM Testbench Puzzles: Tricky Q&A
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
Loading lesson

←UVM Phases and Objections
  1. Topics
  2. DV Interview Puzzles
  3. UVM Testbench Puzzles
  4. UVM Phases and Objections
  5. PASSED Banner Printed Before the Error
On this page

    VLSI DV Interview PuzzlesAll levels

    PASSED Banner Printed Before the Error

    UVM 1.2. The scoreboard prints its verdict in report_phase using the report server's error count. The env (the scoreboard's parent) finds a leftover-state problem and calls `uvm_error` in its own report_phase. What does the log show, and how do you restructure so the verdict is trustworthy?

    Puzzle

    Difficulty: Medium · Puzzle 3 of 6 · Topic: UVM Phases and Objections

    UVM 1.2. The scoreboard prints its verdict in report_phase using the report server's error count. The env (the scoreboard's parent) finds a leftover-state problem and calls `uvm_error` in its own report_phase. What does the log show, and how do you restructure so the verdict is trustworthy?

    Code

    design.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    class my_sb extends uvm_scoreboard;
      `uvm_component_utils(my_sb)
      function new(string name, uvm_component parent); super.new(name, parent); endfunction
      function void report_phase(uvm_phase phase);
        uvm_report_server rs = uvm_report_server::get_server();
        if (rs.get_severity_count(UVM_ERROR) == 0) `uvm_info("SB", "TEST PASSED", UVM_NONE)
        else `uvm_info("SB", "TEST FAILED", UVM_NONE)
      endfunction
    endclass
    
    class my_env extends uvm_env;
      `uvm_component_utils(my_env)
      int leftover;
      function new(string name, uvm_component parent); super.new(name, parent); endfunction
      function void report_phase(uvm_phase phase);
        if (leftover != 0) `uvm_error("ENV", "leftover state at end of test")
      endfunction
    endclass

    Hint

    Which of the two report_phase functions runs first, the parent's or the child's?

    Step-by-step solution

    Diagram
    1) report_phase is bottom-up: the scoreboard (child) runs before the env (parent).
    2) At the scoreboard's report_phase the error count is still 0, so it prints TEST PASSED.
    3) Then the env's report_phase raises the UVM_ERROR, so the log ends with a PASSED banner followed by an ERROR.
    4) Fix: do every check that can fail in check_phase (which finishes for all components before any report_phase starts) and keep report_phase for printing; or print the verdict once from the test's own report_phase, which runs last among the report_phase calls.

    Answer

    Answer: The log shows TEST PASSED first and the UVM_ERROR after it, because the child's report_phase runs before the parent's; move the checks to check_phase.

    How this was checked

    Not run here: The UVM library is not installed here, so this cannot be executed; uvm_report_server, uvm_error and the phase scheduler are UVM library behaviour; the bottom-up versus top-down order it relies on is the one executed in uvm-phase-01.. The answer follows the language rules and the solution steps above.

    Why candidates get it wrong

    Deciding pass/fail in a report_phase that other components may still add errors to: bottom-up order means the child sees only the errors of components that ran before it, not those of its ancestors.

    Interviewer follow-up

    Where would an error raised in final_phase appear relative to a PASSED banner printed in report_phase? Model answer: after it, since final_phase starts only after all report_phase calls are done; the report server's end-of-run summary (counts) is printed later still, so the summary count includes that error even though the banner does not.

    Related topics

    • Back to UVM Phases and Objections

    • UVM Testbench Puzzles section

    Previous

    213 / 293

    Next: Derived build_phase Without super

    Up next

    Up nextDerived build_phase Without super

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Which Way Do the Phases Walk the Tree
    • phase_ready_to_end Never Extends
    • Creating a Component After Build