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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
    • UVM Phases and Objections
    • Factory and config_db
      • Virtual Interface Set with a Relative Path from Top
      • Child Set Later, Parent Set Wins
      • Config Object Set as Base, Got as Derived
      • Config Set Too Late for build_phase
      • Factory Instance Override Path: Relative or Full
      • Override of a Parameterized Component
    • Sequences and Sequencers
    • Analysis, Scoreboards and RAL
    • UVM Testbench Puzzles: Tricky Q&A
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←UVM Testbench Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. UVM Testbench Puzzles
  4. Factory and config_db
On this page

    VLSI DV Interview PuzzlesAll levels

    Factory and config_db

    Configuration problems rarely fail loudly: a path, a type parameter or a phase is slightly off and get() returns 0, or an override never matches. These puzzles drill precedence, scope paths, type keys and timing for uvm_config_db and the factory (UVM 1.2).

    • 6topics
    • 6lessons

    Topics in this section

    1. 1Virtual Interface Set with a Relative Path from Top1 lesson
    2. 2Child Set Later, Parent Set Wins1 lesson
    3. 3Config Object Set as Base, Got as Derived1 lesson
    4. 4Config Set Too Late for build_phase1 lesson
    5. 5Factory Instance Override Path: Relative or Full1 lesson
    6. 6Override of a Parameterized Component1 lesson

    About this puzzle set

    Configuration problems rarely fail loudly: a path, a type parameter or a phase is slightly off and get() returns 0, or an override never matches. These puzzles drill precedence, scope paths, type keys and timing for uvm_config_db and the factory (UVM 1.2).

    Puzzles in this topic

    Diagram
    1. Virtual Interface Set with a Relative Path from Top  [Easy]
    2. Child Set Later, Parent Set Wins  [Medium]
    3. Config Object Set as Base, Got as Derived  [Hard]
    4. Config Set Too Late for build_phase  [Easy]
    5. Factory Instance Override Path: Relative or Full  [Medium]
    6. Override of a Parameterized Component  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    VLSI DV interview puzzle flow

    Diagram
    VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
    
    puzzle prompt
        |
        v
    requirements decode --> constraints/assumptions --> solve strategy
             |                          |                     |
             |                          v                     v
             +------------------> corner cases ---------> final answer
                                         |
                                         v
                                  explain trade-offs
    
    Use section visuals when available; fallback preserves reasoning flow.

    Related topics

    • UVM Testbench Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Virtual Interface Set with a Relative Path from Top

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    Up nextVirtual Interface Set with a Relative Path from Top

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    See also

    • UVM Phases and Objections
    • Sequences and Sequencers
    • Analysis, Scoreboards and RAL