The sequence/driver handshake, arbitration and sequence start-up hide time-zero hangs, wrong exit times and tautological constraints. The puzzles are about what finish_item, grab, p_sequencer and default sequences really do in UVM 1.2.
1. try_next_item Loop That Never Lets Time Pass [Easy]
2. When finish_item Returns [Medium]
3. lock Versus grab Ordering [Medium]
4. Inline Constraint That Constrains Nothing [Medium]
5. Virtual Sequence Started With null [Easy]
6. Default Sequence Ends at Time Zero [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
VLSI DV INTERVIEW PUZZLES OVERVIEW (fallback)
puzzle prompt
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v
requirements decode --> constraints/assumptions --> solve strategy
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+------------------> corner cases ---------> final answer
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v
explain trade-offs
Use section visuals when available; fallback preserves reasoning flow.