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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
    • UVM Phases and Objections
    • Factory and config_db
    • Sequences and Sequencers
      • try_next_item Loop That Never Lets Time Pass
      • When finish_item Returns
      • lock Versus grab Ordering
      • Inline Constraint That Constrains Nothing
      • Virtual Sequence Started With null
      • Default Sequence Ends at Time Zero
    • Analysis, Scoreboards and RAL
    • UVM Testbench Puzzles: Tricky Q&A
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Sequences and Sequencers
  1. Topics
  2. DV Interview Puzzles
  3. UVM Testbench Puzzles
  4. Sequences and Sequencers
  5. try_next_item Loop That Never Lets Time Pass
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    VLSI DV Interview PuzzlesAll levels

    try_next_item Loop That Never Lets Time Pass

    UVM 1.2. A driver polls for items with try_next_item so it can drive idle cycles. At the start no sequence has an item ready. What does the simulation do?

    Puzzle

    Difficulty: Easy · Puzzle 1 of 6 · Topic: Sequences and Sequencers

    UVM 1.2. A driver polls for items with try_next_item so it can drive idle cycles. At the start no sequence has an item ready. What does the simulation do?

    Code

    design.sv
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    task run_phase(uvm_phase phase);
      forever begin
        seq_item_port.try_next_item(req);
        if (req != null) begin
          drive(req);
          seq_item_port.item_done();
        end
      end
    endtask

    Hint

    What does try_next_item do when nothing is waiting, and does the loop contain any wait?

    Step-by-step solution

    Diagram
    1) try_next_item is non-blocking: if no item is available it returns at once with req == null (get_next_item would block instead).
    2) The else path of the loop contains no delay or event wait, so the forever loop spins in zero time.
    3) Simulation time never advances, so the sequence (which needs time to start) can not run, nothing is ever produced, and the simulator hangs at time 0. A UVM timeout does not help because it is a simulation-time timeout.
    4) Fix: in the null case wait for a clock edge (`@(vif.cb)` or `#1`) and drive the idle value, or just use get_next_item when idle driving is not required.

    Answer

    Answer: A zero-time infinite loop: time stays at 0 and the simulation hangs; add a clock wait in the null branch (or use get_next_item).

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. Hand-written model of the documented UVM 1.2 behaviour in plain SystemVerilog (Verilator), not the UVM library: a mailbox try_get loop stands for try_next_item: with no wait in the empty branch 1000 iterations take 0 time; with a delay the item that arrives at 35 is seen at 40.

    Why candidates get it wrong

    The classic hang-with-no-log: a UVM timeout can not rescue it, because the watchdog counts simulation time and the loop never lets time advance.

    Interviewer follow-up

    If items are present, does the loop above still behave? Model answer: yes for the item path (drive() consumes time, item_done releases the sequence), but every time the queue is empty the loop spins again with no wait, so any idle gap reproduces the hang; the idle branch must always consume time.

    Related topics

    • Back to Sequences and Sequencers

    • UVM Testbench Puzzles section

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    See also

    • lock Versus grab Ordering
    • Inline Constraint That Constrains Nothing
    • Virtual Sequence Started With null